A Search Framework That Optimizes Hybrid-Device IMC Architectures For DNNs, Using Chiplets


A technical paper titled “HyDe: A Hybrid PCM/FeFET/SRAM Device-search for Optimizing Area and Energy-efficiencies in Analog IMC Platforms” was published by researchers at Yale University. Abstract: "Today, there are a plethora of In-Memory Computing (IMC) devices- SRAMs, PCMs & FeFETs, that emulate convolutions on crossbar-arrays with high throughput. Each IMC device offers its own pr... » read more

A Chiplet-Based FHE Accelerator Design Enabling Scalability And Higher Throughput


A technical paper titled “REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption” was published by researchers at Graz University of Technology and Samsung Advanced Institute of Technology. Abstract: "Fully Homomorphic Encryption (FHE) has emerged as a promising technology for processing encrypted data without the need for decryption. Despite its potential, its... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing


Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

DAC 2023: Megatrends And The Road Ahead For Design Automation


As Silicon Valley is in the midst of the heat wave the world is experiencing, the recent Design Automation Conference and its exhibition discussed hot technologies. Three megatrends defined the current situation – artificial intelligence (AI), chiplets, and integration. To me, the more exciting aspect of DAC was the discussion of what is ahead for EDA in the decade to come, and for that, the ... » read more

New Technology Accelerates Multi-Die System Simulation


AI-powered chatbots. Robotic manufacturing equipment. Self-driving cars. Bandwidth-intensive applications like these are flourishing—and driving the move from monolithic system-on-chips (SoCs) to multi-die systems. By integrating multiple dies, or chiplets, into a single package, designers can achieve scaling of system functionality at reduced risk and with faster time to market. Multi-die... » read more

Smarter Systems Through Heterogeneous Integration: Highlights From 3D & Systems Summit


It has taken decades of research and development and strong commitment to various industry programs, but the stars are finally aligning for 3D semiconductor systems. No one could have left the 3D & Systems Summit 2023 – held in late June in Dresden – with any doubt that heterogeneous integration, enabled by increasingly mature 3D packaging technologies, is becoming a key driver of the s... » read more

A Chiplet-Based Supercomputer For Generative LLMs That Optimizes Total Cost of Ownership


A technical paper titled "Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models" was published by researchers at University of Washington and University of Sydney. Abstract: "Large language models (LLMs) such as ChatGPT have demonstrated unprecedented capabilities in multiple AI tasks. However, hardware inefficiencies have become a significant factor limiting ... » read more

Getting Rid Of Heat In Chips


Power consumed by semiconductors creates heat, which must be removed from the device, but how to do this efficiently is a growing challenge. Heat is the waste product of semiconductors. It is produced when power is dissipated in devices and along wires. Power is consumed when devices switch, meaning that it is dependent upon activity, and that power is constantly being wasted by imperfect de... » read more

Megatrends At DAC


Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet integration, and heterogeneous integration in an SoC and package. Frank Schirrmeister, vice president solutions and business development at Arteris IP, talks about a variety of topics that fit under the DAC umbrella... » read more

The Future Of Chiplet Reliability


Chipmakers are increasingly turning to advanced packaging to overcome the reticle size limit of silicon manufacturing without increasing transistor density. This method also allows hybrid devices with dies in different process nodes while improving yield, which decreases exponentially with size. However, 2.5D/3D designs introduce a fair share of new challenges, one of the most significant be... » read more

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