Heterogeneous Integration Issues And Developments


There are a slew of new developments in advanced packaging, from new materials, chiplets, and interconnect schemes, to challenges involving how to physically put chips in a package, metallization, thermal cycling, and parasitics in the interconnect path. Dick Otte, CEO of Promex Industries, talks about how this will change chip design and manufacturing, and how those changes are likely to unfol... » read more

3D-IC Reliability Degrades With Increasing Temperature


The reliability of 3D-IC designs is dependent upon the ability of engineering teams to control heat, which can significantly degrade performance and accelerate circuit aging. While heat has been problematic in semiconductor design since at least 28nm, it is much more challenging to deal with inside a 3D package, where electromigration can spread to multiple chips on multiple levels. “Be... » read more

Edge AI And Chiplets


In the near future, more edge artificial intelligence (AI) solutions will find their way into our lives. This will be especially true in the private sector for applications in the field of voice input and analysis of camera data, which will become well-established. These application areas require powerful AI hardware to be able to process the corresponding continuously accumulating data volumes... » read more

Challenges With Adaptive Control


Historically, the performance and power consumption of a system was controlled by what could be done at design time, but chips today are becoming a lot more adaptive. This has become a necessity for cutting edge nodes, but also provides a lot of additional benefits at the expense of greater complexity and verification challenges. Design margins are a tradeoff between performance and yield. C... » read more

An Arrangement of Chiplets That Outperforms A Grid Arrangement (ETH Zurich / U. of Bologna)


A research paper titled "HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement" was published by researchers at ETH Zurich and University of Bologna. Abstract: "2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects ... » read more

Hardware Trojans Target Coherence Systems in Chiplets (Texas A&M / NYU)


A technical paper titled "Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems" was published by researchers at Texas A&M University and NYU. Abstract: "As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communic... » read more

Is UCIe Really Universal?


Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

Addressing Three Big Challenges In Silicon Realization


There is no better way to gain insight into prevailing technical challenges than bringing together industry experts to share experiences and proposed solutions. Silicon realization—the ability to design and build today’s complex semiconductors—is one domain with no shortage of challenges. The quest for the best power, performance, and area, and delivery of first-time-right silicon, requir... » read more

Where All The Semiconductor Investments Are Going


Companies and countries are funneling huge sums of money into semiconductor manufacturing, materials, and research — at least a half-trillion dollars over the next decade, and maybe much more — to guarantee a steady supply of chips and know-how to support growth across a wide swath of increasingly data-centric industries. The build-out of a duplicate supply chain that can guarantee capac... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm


Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

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