tag: chiplets

New Approaches For Processor Architectures
By Ed Sperling - 26 Aug, 2021 - Comments: 0

Processor vendors are starting to emphasize microarchitectural improvements and data movement over process node scaling, setting the stage for much bigger performance gains in devices that narrowly target what end users are trying to accomplish. The changes are a recognition that domain specificity, and the ability to adjust or adapt designs to unique workloads, are now the best way to impro... » read more

How Chips Will Change Health Care
By Ed Sperling - 25 Aug, 2021 - Comments: 0

Jo De Boeck, chief strategy officer and executive vice president at imec, sat down with Semiconductor Engineering to talk about the intersection of medical and semiconductor technology, what's changing in how chips are being used, and what will happen in the short term and long-term. What follows are excerpts of that discussion. SE: Medical technology never advanced at the rate everybody... » read more

Inside Intel’s Ambitious Roadmap
By Mark LaPedus and Ed Sperling - 23 Aug, 2021 - Comments: 2

Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion. SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. Wit... » read more

Ultra-Small Fan-Out Packaging Solution
By Ken Hsiao - 19 Aug, 2021 - Comments: 0

With the advent of the Internet and multimedia, electronics miniaturization in the form of integrated circuits has become an indispensable part of our lives. To ensure its long-term operation and reliability, the rapid development of integrated circuits depends on advancements in not only the design and manufacturing of chips, but also its packaging. As the market demand for consumer and com... » read more

Piecing Together Chiplets
By Mark LaPedus - 22 Jul, 2021 - Comments: 3

Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Behind The Intel-GlobalFoundries Rumor
By Ed Sperling - 19 Jul, 2021 - Comments: 5

A Wall Street Journal report that Intel is looking to buy GlobalFoundries has sparked discussions across the industry. But what exactly this would mean, and why now versus a couple years ago, needs some context. There are layers upon layers of irony behind this would-be deal, and it dates back decades to some rather famous encounters. Consider former AMD CEO Jerry Sanders' 1991 comment that ... » read more

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets
By Ed Sperling - 14 Jul, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, longer IC lifetimes, and a spike in the number of end applications with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; an... » read more

Chipmakers Getting Serious About Integrated Photonics
By Brian Bailey - 12 Jul, 2021 - Comments: 3

Integrating photonics into semiconductors is gaining traction, particularly in heterogeneous multi-die packages, as chipmakers search for new ways to overcome power limitations and deal with increasing volumes of data. Power has been a growing concern since the end of Dennard scaling, which happened somewhere around the 90nm node. There are more transistors per mm², and the wires are thinne... » read more

Shifting Left: Early Multi Physics Analysis For STCO
By Per Viklund - 24 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the emergence of a system technology co-optimization (STCO) approach, in which an SoC is disaggregated into smaller modules (also known as chiplets) that can be asynchronously desi... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging
By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

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