Trustworthy Electronics

By Roland Jancke - 11 Jun, 2020 - Comments: 0

Global supplier networks are a key feature of the development of integrated electronic components today. Even in times of ever more complex trade relationships, supply chains must still function effectively. At the same time, it is necessary to achieve the technological advances required for the development of new products and maintain technological sovereignty. In view of the increasing dig... » read more

New Approaches For Dealing With Thermal Problems

By Ann Mutschler - 11 Jun, 2020 - Comments: 0

New thermal monitoring, simulation and analysis techniques are beginning to coalesce in chips developed at leading-edge nodes and in advanced packages in order to keep those devices running at optimal temperatures. This is particularly important in applications such as AI, automotive, data centers and 5G. Heat can kill a chip, but it also can cause more subtle effects such as premature aging... » read more

Fundamental Changes In Economics Of Chip Security

By Ed Sperling - 10 Jun, 2020 - Comments: 0

Protecting chips from cyberattacks is becoming more difficult, more expensive and much more resource-intensive, but it also is becoming increasingly necessary as some of those chips end up in mission-critical servers and in safety-critical applications such as automotive. Security has been on the semiconductor industry's radar for at least the past several years, despite spotty progress and ... » read more

The Good And Bad Of Chiplets

By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

Enabling Chiplet And Co-Packaged Optics Architectures With 112G XSR SerDes

By Suresh Andani - 14 May, 2020 - Comments: 0

Conventional chip designs are struggling to achieve the scalability, as well as power, performance, and area (PPA), that are demanded of leading-edge designs. With the slowing of Moore’s Law, high complexity ASICs increasingly bump up against reticle limits. The demise of Dennard scaling means power consumption is a growing challenge. In this context, disaggregated architectures such as chipl... » read more

‘More Than Moore’ Reality Check

By Ann Mutschler - 14 May, 2020 - Comments: 1

The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

Re-Imagining The GPU

By Susan Rambo And Ed Sperling - 23 Apr, 2020 - Comments: 0

John Rayfield, CTO at Imagination Technologies, sat down with Semiconductor Engineering to talk about RISC-V, AI, and computing architectures. What follows are excerpts of that conversation. SE: What your plans are for RISC-V? Rayfield: We're actively finalizing the integration of RISC-V cores into future-generation GPUs. That work has been going on for several months. Moving forward, we'... » read more

Scaling At The Angstrom Level

By Ed Sperling - 16 Apr, 2020 - Comments: 0

It now appears likely that 2nm will happen, and possibly the next node or two beyond that. What isn't clear is what those chips will be used for, by whom, and what they ultimately will look like. The uncertainty isn't about the technical challenges. The semiconductor industry understands the implications of every step of the manufacturing process down to the sub-nanometer level, including ho... » read more

Making Chips At 3nm And Beyond

By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Wafer Test Challenges For Chiplets

By Amy Leong - 10 Mar, 2020 - Comments: 0

In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage. From a test perspective, making chiplets a mainstream technology depends on ensuring Good Enough Die at a reasonable test cost. Wafer-level test plays a critical and intricate role in the chipl... » read more

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tag: chiplets

Trustworthy Electronics

New Approaches For Dealing With Thermal Problems

Fundamental Changes In Economics Of Chip Security

The Good And Bad Of Chiplets

Enabling Chiplet And Co-Packaged Optics Architectures With 112G XSR SerDes

‘More Than Moore’ Reality Check

Re-Imagining The GPU

Scaling At The Angstrom Level

Making Chips At 3nm And Beyond

Wafer Test Challenges For Chiplets

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