tag: chiplets

Security Is Critical For Commercial Chiplets
By Ann Mutschler - 13 Mar, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the security issues and requirements in commercial chiplet ecosystem, with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen Slater, EDA prod... » read more

UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel. Abstract: "Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0... » read more

Chiplet IP Standards Are Just The Beginning
By Ann Mutschler - 06 Mar, 2024 - Comments: 2

Experts at the Table: Semiconductor Engineering sat down to talk about chiplet standards, interoperability, and the need for highly customized AI chiplets, with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen S... » read more

Commercial Chiplet Ecosystem May Be A Decade Away
By Ann Mutschler - 29 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the challenges of establishing a commercial chiplet ecosystem with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen Slater, EDA product mana... » read more

Accellera Preps New Standard For Clock-Domain Crossing
By Brian Bailey - 29 Feb, 2024 - Comments: 0

Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit. At the register transfer level (RTL), when a data signal passes between two flip flops, it initially is assumed that clocks are perfect. After clock-tree synthesis and place-and-route are perfor... » read more

Intel, And Others, Inside
By Ed Sperling - 22 Feb, 2024 - Comments: 2

Intel this week made a strong case for how it will regain global process technology leadership, unfurling an aggressive technology and business roadmap that includes everything from several more process node shrinks that ultimately could scale into the single-digit angstrom range to a broad shift in how it approaches the market. Both will be essential for processing the huge amount of data for ... » read more

Why Chiplets Are So Critical In Automotive
By John Koon - 20 Feb, 2024 - Comments: 1

Chiplets are gaining renewed attention in the automotive market, where increasing electrification and intense competition are forcing companies to accelerate their design and production schedules. Electrification has lit a fire under some of the biggest and best-known carmakers, which are struggling to remain competitive in the face of very short market windows and constantly changing requir... » read more

The Seven Pillars Of IC Package Physical Design
By Keith Felton - 15 Feb, 2024 - Comments: 0

Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

IC Package Physical Design Best Practices
By Siemens EDA - 15 Feb, 2024 - Comments: 0

Historically IC package design has been a relatively simple task which allowed the die bumps to be fanned out on a package substrate to a floorplan geometry suitable for connecting to a printed circuit board (PCB). But today the industry is moving to disaggregation of traditional monolithic SoC functions into chiplets often interfaced with local high-speed memory to avoid silicon reticle limits... » read more

Hidden Costs And Tradeoffs In IC Quality
By Gregory Haley - 08 Feb, 2024 - Comments: 0

Balancing reliability against cost is becoming more difficult for semiconductor test, as chip complexity increases and devices become more domain-specific. Tests need to be efficient and effective without breaking the bank, while also ensuring chips are of sufficient quality for their specific application. The problem is that every new IC device adds its own set of challenges, from smaller f... » read more

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