tag: chiplets

Silicon Photonic Interconnected Chiplets With Computational Network And IMC For LLM Inference Acceleration (NUS)
By Technical Paper Link - 10 Nov, 2025 - Comments: 0

A new technical paper titled "PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration" was published by researchers at the National University of Singapore. Abstract "This paper presents a 3D-stacked chiplets based large language model (LLM) inference accelerator, consisting of non-volatile in-memory-computing proces... » read more

Co-Simulation Framework for Parallel DNN Execution on Chiplet-Based Systems (UW–Madison, Washington State)
By Technical Paper Link - 03 Nov, 2025 - Comments: 0

A new technical paper titled "CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems" was published by researchers at University of Wisconsin–Madison and Washington State University. Abstract "Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as ra... » read more

Utilizing Chiplet-Locality For Efficient Memory Mapping In MCM GPUs (ETRI, Sungkyunkwan Univ.)
By Technical Paper Link - 30 Oct, 2025 - Comments: 0

A new technical paper titled "Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs" was published by researchers at Electronics and Telecommunications Research Institute (ETRI) and Sungkyunkwan University. Abstract "While the multi-chip module (MCM) design allows GPUs to scale compute and memory capabilities through multi-chip integration, it introduces memory ... » read more

Ensuring Reliability Becomes Harder In Multi-Die Assemblies
By Gregory Haley - 29 Oct, 2025 - Comments: 0

Multi-die assemblies are bringing together a variety of materials and processes with distinctly different physical properties, creating significant challenges in manufacturing and packaging that can impact yield at time zero and reliability in the field. What passes electrical screening at the end of the line may look good on paper, but these devices can still fail once exposed to rapid and ... » read more

Developing RISC-V Compute Subsystems
By Baya Systems - 29 Oct, 2025 - Comments: 0

As demand grows for scalable, efficient, and customized compute, more companies are turning to RISC-V as the preferred architecture for high-performance computing. Tenstorrent and Baya Systems have designed a compute subsystem combining IP from both companies designed to enable AI and HPC use cases. The solution leverages Tenstorrent’s Ascalon processor and Baya’s advanced interconnect tech... » read more

In-System Test For AI Data Centers
By Ed Sperling - 20 Oct, 2025 - Comments: 0

Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

Integrated Modular Firmware Solutions: A Vital Component Of Custom Silicon Chiplet Architecture Designs
By Marc Meunier - 16 Oct, 2025 - Comments: 0

By Marc Meunier and Srini Narayana The shift from monolithic SoC designs to chiplet-based architecture isn’t just a packaging innovation. It’s a fundamental rethinking of how custom silicon is designed, manufactured, and deployed. This transition is driven by the growing impracticality of scaling large monolithic dies at advanced nodes. As die sizes increase, so do the costs, yield ri... » read more

Using AI/ML To Find And Correlate IC Test Data
By Ed Sperling - 15 Oct, 2025 - Comments: 0

What causes low yield in wafers? Usually it's due to design or process changes, but sometimes yield issues occur even if there haven't been any changes from one manufacturing lot to the next. Finding the cause requires some sleuthing, and the best approach for pinpointing problems is to mine design, process, and manufacturing data, and to correlate that data by date and time, by which equipment... » read more

EBook: Helping To Realize Chiplet Ambitions
By Cadence - 15 Oct, 2025 - Comments: 0

The future of physical AI, from autonomous vehicles to robotics and aerospace, depends on overcoming the limitations of monolithic SoCs. As computing demands grow, a shift to scalable, modular, and reusable chiplet-based architectures is essential. This transition presents new challenges, from ensuring interoperability to managing complex system-level integration. How can you navigate this land... » read more

Microelectronics and Advanced Packaging Technologies Roadmap 2.0 (SRC)
By Technical Paper Link - 14 Oct, 2025 - Comments: 0

The Semiconductor Research Corporation just released its Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap 2.0, a comprehensive update to the industry’s first 3D semiconductor roadmap. The roadmap includes contributions of over 370 experts from 132 organizations, with updated content and a new chapter on digital twins and their applications. The roadmap was funded by the ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy