The Future Of SoC Design Is Data Movement


The semiconductor industry is experiencing rapid advances in chiplet adoption, high-bandwidth memory, Compute Express Link (CXL) fabrics, and automotive zonal architectures. As we move into the second half of 2025, the only sustainable path forward is a layered, physically aware, and automated interconnect methodology that can keep pace with escalating complexity. This article is Part Two of... » read more

First Forays Into True 3D-IC Designs


Experts at the Table: Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager... » read more

Benefits And Challenges Of Using Chiplets


The move to chiplets opens the door to more features than can be packed into a reticle-sized SoC. That potentially means more processing power, simpler designs, and higher yields. But it's not as simple as swapping LEGO blocks into a chassis. Ashley Stevens, director of product management and marketing at Arteris, talks with Semiconductor Engineering about the challenges of using coherent versu... » read more

The Future Of Verification


Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

Mitigating Warpage In Multi-Chiplet Systems


Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

Collaboration Is Key To Growing Semiconductor Industry


John Kibarian, CEO and co-founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, will deliver a keynote during the CEO Summit at SEMICON West in October titled “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms.” He recently shared with me a summary of what his talk will cover and his perspective on why collabora... » read more

New Demands For IP Reuse


Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight;... » read more

The Need for System-Technology Co-Optimization (STCO)


Modern semiconductor components are becoming more and more complex and cost sensitive. To master technological and economic challenges, new chiplet approaches and heterogeneous integration technologies are becoming increasingly relevant. This, in turn, calls for new heterogeneous design approaches. They make it possible to combine different design domains across technological options while sati... » read more

From Discovery To High-Speed Delivery: A Unified Verification Approach For UCIe 3.0 Features And Manageability


By Ujjwal Negi and Prashant Dixit The Universal Chiplet Interconnect Express (UCIe) standard is redefining multi-die integration, enabling high-performance, scalable connections between heterogeneous chiplets. UCIe 2.0 introduced a dedicated manageability layer — a control plane for configuring, monitoring, and coordinating chiplet management elements independently from mainband and sideba... » read more

Verifying The Evolving UCIe Landscape


This paper details a verification strategy for UCIe 3.0 designs, integrating both legacy manageability architecture and emerging UCIe 3.0 features into a reusable, scalable framework. Built on a layered UVM architecture, Questa One Avery VIP for UCIe enables flexible modeling of complex domains through configurable APIs and supports automated discovery and routing table setup for both direct an... » read more

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