tag: chiplets

Mitigating Warpage In Multi-Chiplet Systems
By Laura Peters - 22 Sep, 2025 - Comments: 0

Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

Collaboration Is Key To Growing Semiconductor Industry
By Bob Smith - 18 Sep, 2025 - Comments: 0

John Kibarian, CEO and co-founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, will deliver a keynote during the CEO Summit at SEMICON West in October titled “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms.” He recently shared with me a summary of what his talk will cover and his perspective on why collabora... » read more

New Demands For IP Reuse
By Brian Bailey - 17 Sep, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight;... » read more

The Need for System-Technology Co-Optimization (STCO)
By Benjamin Prautsch - 11 Sep, 2025 - Comments: 0

Modern semiconductor components are becoming more and more complex and cost sensitive. To master technological and economic challenges, new chiplet approaches and heterogeneous integration technologies are becoming increasingly relevant. This, in turn, calls for new heterogeneous design approaches. They make it possible to combine different design domains across technological options while sati... » read more

From Discovery To High-Speed Delivery: A Unified Verification Approach For UCIe 3.0 Features And Manageability
By Ujjwal Negi - 11 Sep, 2025 - Comments: 0

By Ujjwal Negi and Prashant Dixit The Universal Chiplet Interconnect Express (UCIe) standard is redefining multi-die integration, enabling high-performance, scalable connections between heterogeneous chiplets. UCIe 2.0 introduced a dedicated manageability layer — a control plane for configuring, monitoring, and coordinating chiplet management elements independently from mainband and sideba... » read more

Verifying The Evolving UCIe Landscape
By Siemens EDA - 10 Sep, 2025 - Comments: 0

This paper details a verification strategy for UCIe 3.0 designs, integrating both legacy manageability architecture and emerging UCIe 3.0 features into a reusable, scalable framework. Built on a layered UVM architecture, Questa One Avery VIP for UCIe enables flexible modeling of complex domains through configurable APIs and supports automated discovery and routing table setup for both direct an... » read more

Data Feed Forward And How It Works: Part 2
By Roberto Colecchia - 09 Sep, 2025 - Comments: 0

As chiplets and advanced packaging redefine semiconductor architecture, managing complexity isn’t just about the silicon—it’s about the data. Modern multi-die packages often contain components from different vendors, integrated in 2.5D or 3D configurations. Each die brings its own risks, and diagnosing issues after assembly is increasingly difficult—especially when data isn’t share... » read more

LLM-Based Chiplet Design Generation Framework (Univ. of Minnesota)
By Technical Paper Link - 29 Aug, 2025 - Comments: 0

A new technical paper titled "MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging" was published by researchers at the University of Minnesota - Twin Cities. Abstract "As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and memory hierarch... » read more

Chiplet Design Considerations
By Robert Kruger - 28 Aug, 2025 - Comments: 0

Chiplets are a way to offer continuing increases in compute capacity and I/O bandwidth needs by splitting SoC functionality into smaller heterogeneous or homogeneous dies called chiplets and integrating these chiplets into a single system in package (SIP), where the total silicon content can exceed the reticle size of a single SoC. SIP includes traditional package substrates but also may includ... » read more

A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
By Andy Nightingale - 28 Aug, 2025 - Comments: 0

The rise of artificial intelligence (AI) is advancing at breakneck speed, pushing computing demands. At the same time, Moore’s Law slows, making monolithic devices increasingly cost-prohibitive and harder to scale. As traditional monolithic scaling hits the wall, the solution is to disaggregate the design into multiple dies, known as chiplets. These chiplets are mounted on a common substrate ... » read more

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