tag: chiplets

Thermally-Aware, Multi-Objective Scheduling Framework for DL Workloads on Heterogeneous Multi-Chiplet PIM Architectures (UW–Madison, Washington State)
By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures" was published by researchers at the University of Wisconsin–Madison and Washington State University. Abstract "Chiplet-based integration enables large-scale systems that combine diverse technologies, enabling higher yield, lower costs, and sca... » read more

Launching The Full Potential Of 3D IC With Front-End Architectural Planning
By Siemens EDA - 19 Aug, 2025 - Comments: 0

3D IC and chiplet-based design have the potential to accelerate the pace of semiconductor industry innovation. 3D IC design teams pack more functionality closer together and achieve higher levels of systems integration and performance in a smaller footprint faster than what’s possible with traditional SoC implementation. To achieve the full potential of 3D IC, teams need cost-effective fro... » read more

Transforming Test For Co-packaged Optics
By Laura Peters - 12 Aug, 2025 - Comments: 0

Data centers are undergoing a dramatic transformation to reduce the power consumption of high-speed data transmissions by 70% or more with co-packaged optics. By moving optical transceivers from the fronts of racks into the same package as the networking switch and HBMs, AI programs that used to take a week to run can now be completed in a day. To enable this change in production manufacturi... » read more

Chiplet Interfaces Embrace Failures
By Anne Meixner - 12 Aug, 2025 - Comments: 0

Redundancy in chiplet interfaces is now a prerequisite for achieving sufficient yield in high-performance computing devices, which today are packed with tens of thousands of interconnects. And as the number and density of those interconnects increases, the prospects for yield only worsen. For more than two decades, high-speed I/O interfaces have included reliability strategies to manage in-f... » read more

Streamlining Functional Verification For Multi-Die And Chiplet Designs
By Cadence - 30 Jul, 2025 - Comments: 0

An Opportunity and a Challenge The manufacturing aspects of multi-die/multi-chiplet designs are often highlighted, but what about verification? Functional correctness and performance of inter-die connections via a standard interface, such as UCIe or a custom inter-die interface, are not guaranteed to meet all system requirements. These interfaces must be verified comprehensively, ensuring co... » read more

When Standards Enable Chiplets
By Brian Bailey - 30 Jul, 2025 - Comments: 0

Semiconductor Engineering sat down and discussed the need for standards to enable an ecosystem for chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute Solutions Group; and Rob Kr... » read more

Changes In Scan Test Data
By Ed Sperling - 29 Jul, 2025 - Comments: 0

Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing chipmakers to trade off higher costs with reliability. The solution is to raise the level of abstraction for scan tests, using a bus and packetized data that can run at much higher frequencies than is pos... » read more

Chiplet Ecosystem Slowly Emerges
By Brian Bailey - 23 Jul, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute S... » read more

Questa One Avery VIP: Accelerated Confidence In Complex Protocol Verification
By Siemens EDA - 21 Jul, 2025 - Comments: 0

In today’s rapidly advancing digital landscape, the role of functional verification has never been more critical. As systems become increasingly complex, ensuring their reliability and performance poses significant challenges for both design and verification engineers. The stakes are high; verification failures can lead to costly recalls, safety risks, and damage to brand reputation. The late... » read more

Do We Have Enough Standards For An Open-Chiplet Ecosystem?
By Andy Heinig - 17 Jul, 2025 - Comments: 0

For some time now, the semiconductor industry has been discussing the development of an open chiplet ecosystem. The idea is that, rather than having monolithic systems on a chip, it should be possible to combine smaller, specialized chiplets in a modular way – ideally across different manufacturers. Doing so would promise great flexibility with much shorter development times, resulting in muc... » read more

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