tag: chiplets

Changes In Scan Test Data
By Ed Sperling - 29 Jul, 2025 - Comments: 0

Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing chipmakers to trade off higher costs with reliability. The solution is to raise the level of abstraction for scan tests, using a bus and packetized data that can run at much higher frequencies than is pos... » read more

Chiplet Ecosystem Slowly Emerges
By Brian Bailey - 23 Jul, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute S... » read more

Questa One Avery VIP: Accelerated Confidence In Complex Protocol Verification
By Siemens EDA - 21 Jul, 2025 - Comments: 0

In today’s rapidly advancing digital landscape, the role of functional verification has never been more critical. As systems become increasingly complex, ensuring their reliability and performance poses significant challenges for both design and verification engineers. The stakes are high; verification failures can lead to costly recalls, safety risks, and damage to brand reputation. The late... » read more

Do We Have Enough Standards For An Open-Chiplet Ecosystem?
By Andy Heinig - 17 Jul, 2025 - Comments: 0

For some time now, the semiconductor industry has been discussing the development of an open chiplet ecosystem. The idea is that, rather than having monolithic systems on a chip, it should be possible to combine smaller, specialized chiplets in a modular way – ideally across different manufacturers. Doing so would promise great flexibility with much shorter development times, resulting in muc... » read more

When Can I Buy A Chiplet?
By Brian Bailey - 17 Jul, 2025 - Comments: 1

One year ago, Semiconductor Engineering conducted its first roundtable to find out the true state of the industry for chiplets. At that event, it was stated that no chiplet had ever been reused in a design for which it was not initially intended. How much has changed over the past year? Returning from last year were Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice... » read more

Detailed Study of Performance Modeling For LLM Implementations At Scale (imec)
By Technical Paper Link - 07 Jul, 2025 - Comments: 0

A new technical paper titled "System-performance and cost modeling of Large Language Model training and inference" was published by researchers at imec. Abstract "Large language models (LLMs), based on transformer architectures, have revolutionized numerous domains within artificial intelligence, science, and engineering due to their exceptional scalability and adaptability. However, the ex... » read more

Development and Deployment of 2.5D Multi-Foundry Chiplet Solution Scaling Beyond Multi-Reticle Approaches (Intel)
By Technical Paper Link - 03 Jul, 2025 - Comments: 0

A new technical paper titled "System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution" was published by researchers at Intel Corporation. Abstract "The proliferation of chiplet-based designs, driven by the escalating computational demands of AI, presents unique validation challenges when integrating heterogenous chiplets. This paper investigat... » read more

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Redefining SoC Design: The Shift To Secure Chiplet-Based Architectures
By Moshiko Emmer - 26 Jun, 2025 - Comments: 0

The semiconductor industry is undergoing a paradigm shift from monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This transformation is driven by escalating design complexity, soaring fabrication costs, and the relentless pursuit of efficiency. However, as chiplet adoption accelerates, security becomes a critical concern, requiring robust measures to protect data,... » read more

Are Larger Reticle Sizes On The Horizon?
By Katherine Derbyshire - 19 Jun, 2025 - Comments: 0

Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits or a wholesale change to larger masks. Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6x6-inch to 6x11-inch masks that would eliminate stitching, but it... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy