tag: chiplets

Shaping The Future Of AI Processors: A Tech Threads Conversation With Jim Keller
By Nandan Nayampally - 25 Nov, 2025 - Comments: 0

I had the pleasure of hosting renowned computer architect and Tenstorrent CEO Jim Keller, on the latest episode of Baya Systems’ Tech Threads podcast. If you haven’t already, listen to get his insights on the need for “open” intelligence architectures and what would be needed to drive the semiconductor industry forward. What is an “open” intelligent architecture and ecosystem? As... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

From Bottleneck to Breakthrough: Scalable Fabric IP for High- Bandwidth AI and HPC Systems
By Baya Systems - 24 Nov, 2025 - Comments: 0

As compute density and heterogeneity grow rapidly in modern SoCs targeting high-performance computing (HPC) and artificial intelligence (AI) workloads, efficient data movement has emerged as a critical performance and power bottleneck. With increasing core counts, high-speed accelerators, and complex memory hierarchies, traditional bus and crossbar-based interconnects fail to scale, resulting i... » read more

Chiplet Integration and Testing: Key Lessons for Next-Gen Semiconductor Packaging
By Vineet Pancholi - 20 Nov, 2025 - Comments: 0

The Chiplet Era Has Arrived The floodgates for chiplet-based design have officially opened. Over the past several quarters, manufacturing test flows have been validating 2.5D package architectures, and production volumes are ramping up. These designs promise flexibility and performance, but they also introduce new test sensitivities—electrical, thermal, and mechanical—that challenge tradit... » read more

Silicon Photonic Interconnected Chiplets With Computational Network And IMC For LLM Inference Acceleration (NUS)
By Technical Paper Link - 10 Nov, 2025 - Comments: 0

A new technical paper titled "PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration" was published by researchers at the National University of Singapore. Abstract "This paper presents a 3D-stacked chiplets based large language model (LLM) inference accelerator, consisting of non-volatile in-memory-computing proces... » read more

Co-Simulation Framework for Parallel DNN Execution on Chiplet-Based Systems (UW–Madison, Washington State)
By Technical Paper Link - 03 Nov, 2025 - Comments: 0

A new technical paper titled "CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems" was published by researchers at University of Wisconsin–Madison and Washington State University. Abstract "Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as ra... » read more

Utilizing Chiplet-Locality For Efficient Memory Mapping In MCM GPUs (ETRI, Sungkyunkwan Univ.)
By Technical Paper Link - 30 Oct, 2025 - Comments: 0

A new technical paper titled "Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs" was published by researchers at Electronics and Telecommunications Research Institute (ETRI) and Sungkyunkwan University. Abstract "While the multi-chip module (MCM) design allows GPUs to scale compute and memory capabilities through multi-chip integration, it introduces memory ... » read more

Ensuring Reliability Becomes Harder In Multi-Die Assemblies
By Gregory Haley - 29 Oct, 2025 - Comments: 0

Multi-die assemblies are bringing together a variety of materials and processes with distinctly different physical properties, creating significant challenges in manufacturing and packaging that can impact yield at time zero and reliability in the field. What passes electrical screening at the end of the line may look good on paper, but these devices can still fail once exposed to rapid and ... » read more

Developing RISC-V Compute Subsystems
By Baya Systems - 29 Oct, 2025 - Comments: 0

As demand grows for scalable, efficient, and customized compute, more companies are turning to RISC-V as the preferred architecture for high-performance computing. Tenstorrent and Baya Systems have designed a compute subsystem combining IP from both companies designed to enable AI and HPC use cases. The solution leverages Tenstorrent’s Ascalon processor and Baya’s advanced interconnect tech... » read more

In-System Test For AI Data Centers
By Ed Sperling - 20 Oct, 2025 - Comments: 0

Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

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