tag: chiplets

What’s Next for 2.5D Packaging?
By Bryon Moyer - 18 Dec, 2025 - Comments: 0

Interposers and bridges, two of the key elements for interconnecting multiple chips and chiplets in an advanced package, are undergoing fundamental changes in how they're built and assembled. Interposers are becoming thicker and more complex, while bridges are being used to reduce the assembled cost. Both efforts are facing new challenges. Interposers are effectively platforms on which mu... » read more

AI Buildout Makes HPC Simulation More Challenging
By Ann Mutschler - 11 Dec, 2025 - Comments: 0

Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

Chiplets Vs. Soft IP: Different In Almost Every Way
By Bryon Moyer - 11 Dec, 2025 - Comments: 2

Chiplets serve a similar function as the soft IP widely used in chips today, but the similarities end there. While both can speed time to market and enable design teams to focus limited resources where they can best be applied, the implementation, manufacturing, test, and long-term business requirements wrought by a chiplet marketplace would be very different. Soft IP (also known as RTL IP) ... » read more

3DKs: Making Headway On Chiplet Standards
By Laura Peters - 01 Dec, 2025 - Comments: 0

The chiplet model has been proven by the early adopters. Large companies that successfully developed chips at leading nodes have integrated multiple chiplets into systems, where the entire silicon cycle is performed in-house. But the industry’s long-term goal of a free and open chiplet marketplace, in which companies of any size can reap the rewards and economies of scale associated with mult... » read more

Simplifying ESD Protection and Inter-Chiplet Signaling In Future 2.5D/3D Packaging Technologies (Arizona State, Univ. of Minnesota)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity" was published by researchers at Arizona State University and University of Minnesota. Abstract: "The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction... » read more

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond" was published by researchers at ETH Zurich and University of Bologna. Abstract: "We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the f... » read more

Shaping The Future Of AI Processors: A Tech Threads Conversation With Jim Keller
By Nandan Nayampally - 25 Nov, 2025 - Comments: 0

I had the pleasure of hosting renowned computer architect and Tenstorrent CEO Jim Keller, on the latest episode of Baya Systems’ Tech Threads podcast. If you haven’t already, listen to get his insights on the need for “open” intelligence architectures and what would be needed to drive the semiconductor industry forward. What is an “open” intelligent architecture and ecosystem? As... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

From Bottleneck to Breakthrough: Scalable Fabric IP for High- Bandwidth AI and HPC Systems
By Baya Systems - 24 Nov, 2025 - Comments: 0

As compute density and heterogeneity grow rapidly in modern SoCs targeting high-performance computing (HPC) and artificial intelligence (AI) workloads, efficient data movement has emerged as a critical performance and power bottleneck. With increasing core counts, high-speed accelerators, and complex memory hierarchies, traditional bus and crossbar-based interconnects fail to scale, resulting i... » read more

Chiplet Integration and Testing: Key Lessons for Next-Gen Semiconductor Packaging
By Vineet Pancholi - 20 Nov, 2025 - Comments: 0

The Chiplet Era Has Arrived The floodgates for chiplet-based design have officially opened. Over the past several quarters, manufacturing test flows have been validating 2.5D package architectures, and production volumes are ramping up. These designs promise flexibility and performance, but they also introduce new test sensitivities—electrical, thermal, and mechanical—that challenge tradit... » read more

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