tag: chiplets

When To Move To Multi-Die Assemblies
By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

2025 – A Year Of Change And Anticipation
By Brian Bailey - 23 Dec, 2025 - Comments: 0

2025 has certainly been a year of unexpected changes. These had a significant impact on the semiconductor industry and everything that supports it. Not all the changes have been bad, but flexibility has been a requirement for continued success or to make the most of an opportunity provided. Some industries, such as aerospace and defense, are seeing a significant boost around the world. Data ... » read more

Thermal Modeling in Emerging Heterogeneous 2.5D/3D Systems (EPFL, Universidad Complutense de Madrid)
By Technical Paper Link - 22 Dec, 2025 - Comments: 0

A new technical paper titled "3D-ICE 4.0: Accurate and efficient thermal modeling for 2.5D/3D heterogeneous chiplet systems" was published by researchers at EPFL and Universidad Complutense de Madrid. Abstract "The increasing power densities and intricate heat dissipation paths in advanced 2.5D/3D chiplet systems necessitate thermal modeling frameworks that deliver detailed thermal maps w... » read more

Analysis of Thermal and Mechanical Behavior for Advanced Packaging (Sungkyunkwan Univ. et al)
By Technical Paper Link - 19 Dec, 2025 - Comments: 0

A new technical paper titled “A review of the thermo-mechanical analysis framework for microelectronics packaging: Mechanics, material property determination, and structural considerations” was published by researchers at Sungkyunkwan University, Korea Institute of Industrial Technology, Korea University, Seoul National University, and Pukyong National University. Abstract Excerpt “... » read more

What’s Next for 2.5D Packaging?
By Bryon Moyer - 18 Dec, 2025 - Comments: 0

Interposers and bridges, two of the key elements for interconnecting multiple chips and chiplets in an advanced package, are undergoing fundamental changes in how they're built and assembled. Interposers are becoming thicker and more complex, while bridges are being used to reduce the assembled cost. Both efforts are facing new challenges. Interposers are effectively platforms on which mu... » read more

AI Buildout Makes HPC Simulation More Challenging
By Ann Mutschler - 11 Dec, 2025 - Comments: 0

Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

Chiplets Vs. Soft IP: Different In Almost Every Way
By Bryon Moyer - 11 Dec, 2025 - Comments: 2

Chiplets serve a similar function as the soft IP widely used in chips today, but the similarities end there. While both can speed time to market and enable design teams to focus limited resources where they can best be applied, the implementation, manufacturing, test, and long-term business requirements wrought by a chiplet marketplace would be very different. Soft IP (also known as RTL IP) ... » read more

3DKs: Making Headway On Chiplet Standards
By Laura Peters - 01 Dec, 2025 - Comments: 0

The chiplet model has been proven by the early adopters. Large companies that successfully developed chips at leading nodes have integrated multiple chiplets into systems, where the entire silicon cycle is performed in-house. But the industry’s long-term goal of a free and open chiplet marketplace, in which companies of any size can reap the rewards and economies of scale associated with mult... » read more

Simplifying ESD Protection and Inter-Chiplet Signaling In Future 2.5D/3D Packaging Technologies (Arizona State, Univ. of Minnesota)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity" was published by researchers at Arizona State University and University of Minnesota. Abstract: "The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction... » read more

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna)
By Technical Paper Link - 25 Nov, 2025 - Comments: 0

A new technical paper titled "Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond" was published by researchers at ETH Zurich and University of Bologna. Abstract: "We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the f... » read more

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