tag: CMOS

What Goes Around Comes Around: Moore’s Law At 10nm And Beyond
By Greg Yeric - 13 Feb, 2014 - Comments: 2

Modified by Greg Yeric from original by Eric Fischer Gordon Moore penned his famous observation in an era when the people developing the process were also the people designing the circuits. Over time, things got more complicated and work specialization set in, but all was well in the world for many years as the fabs kept delivering on Moore’s Law. Yes, designers had to come up with lot... » read more

The List Of Unknowns Grows After Silicon
By Katherine Derbyshire - 07 Feb, 2014 - Comments: 3

As discussed earlier in this series, most proposed alternative channel schemes depend on germanium channels for pMOS transistors, and InGaAs channels for nMOS transistors. Of the two materials, InGaAs poses by far the more difficult integration challenges. Germanium has been present in advanced silicon CMOS fabs for several technology generations, having been introduced used in strained silicon... » read more

What’s After CMOS?
By Mark LaPedus - 24 Jan, 2014 - Comments: 3

Chipmakers continue to scale the CMOS transistor to finer geometries, but the question is for how much longer. The current thinking is that the CMOS transistor could scale at least to the 3nm node in the 2021 timeframe. And then, CMOS could run out of gas, prompting the need for a new switch technology. So what’s after the CMOS-based transistor? Carbon nanotubes and graphene get the most a... » read more

Experts At The Table: MEMS Challenges
By Mark LaPedus - 13 Dec, 2013 - Comments: 1

Semiconductor Engineering sat down to discuss the challenges of MEMS with Rakesh Kumar, senior director of the MEMS program at GlobalFoundries; Tak Tanaka, managing director for Applied Global Services at Applied Materials; Paul Lindner, executive technology director at EV Group; and Alissa M. Fitzgerald, founder and managing member at A.M. Fitzgerald & Associates. SE: What’s happening... » read more

What’s After 10nm?
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions. Consumers have grown accustomed to the benefits of Moore’s Law, but the question is for how much longer? Chips based ... » read more

Executive Briefing: Soitec CEO
By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss FD-SOI, solar and various technology trends with André-Jacques Auberton-Hervé, chairman and chief executive of Soitec, a supplier of silicon-on-insulator (SOI) substrates, solar concentrators and other products. SMD: The digital process roadmap is moving in several directions. Some pure-play foundries will offer ... » read more

Experts At The Table: Process Technology Challenges
By Mark LaPedus - 13 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

CMOS And SOI Invade RF Front End
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus The next-generation 4G wireless standard known as long-term evolution (LTE) presents some new and difficult design choices for OEMs. One of the more difficult choices involves the less glamorous, but arguably the most critical part in a handset—the radio-frequency (RF) front-end. Typically, the RF front-end often comes in a module and includes various key components, such ... » read more

Designing with FinFETs: The Opportunities and the Challenges
By Various Writers - 28 Feb, 2013 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

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