tag: CMOS

Experts At The Table: MEMS Challenges
By Mark LaPedus - 13 Dec, 2013 - Comments: 1

Semiconductor Engineering sat down to discuss the challenges of MEMS with Rakesh Kumar, senior director of the MEMS program at GlobalFoundries; Tak Tanaka, managing director for Applied Global Services at Applied Materials; Paul Lindner, executive technology director at EV Group; and Alissa M. Fitzgerald, founder and managing member at A.M. Fitzgerald & Associates. SE: What’s happening... » read more

What’s After 10nm?
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions. Consumers have grown accustomed to the benefits of Moore’s Law, but the question is for how much longer? Chips based ... » read more

Executive Briefing: Soitec CEO
By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss FD-SOI, solar and various technology trends with André-Jacques Auberton-Hervé, chairman and chief executive of Soitec, a supplier of silicon-on-insulator (SOI) substrates, solar concentrators and other products. SMD: The digital process roadmap is moving in several directions. Some pure-play foundries will offer ... » read more

Experts At The Table: Process Technology Challenges
By Mark LaPedus - 13 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

CMOS And SOI Invade RF Front End
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus The next-generation 4G wireless standard known as long-term evolution (LTE) presents some new and difficult design choices for OEMs. One of the more difficult choices involves the less glamorous, but arguably the most critical part in a handset—the radio-frequency (RF) front-end. Typically, the RF front-end often comes in a module and includes various key components, such ... » read more

Designing with FinFETs: The Opportunities and the Challenges
By Various Writers - 28 Feb, 2013 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

Smartphones Dial Up New RF Processes
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus The rapid shift towards smartphones and tablets is driving the need for new and low-power chips at finer geometries. Today, the latest application processors, integrated basebands and other digital cell-phone chips are 28nm planar devices. And it won’t be long before OEMs incorporate 20nm planar and finFET devices in their systems as a means to reduce power and extend batt... » read more

The Trouble With FinFETs
By Joanne Itow - 16 Aug, 2012 - Comments: 0

By Joanne Itow The industry’s quest to continue on the semiconductor roadmap defined by Moore’s Law has led to the adoption of a new transistor structure. Whether you call them finFETs, tri-gate or 3D transistors, building these new devices is difficult. But the technology is only half the challenge. In 2002, Chen Ming Hu* spoke at the Semico Summit. The title of his presentation was �... » read more

Inflection Points
By Ed Sperling - 15 Aug, 2012 - Comments: 0

Semiconductor Manufacturing and Design talks with Paul Boudre, chief operating officer at Soitec, about FinFETs, industry inflection points, the end of life for planar transistors, bulk CMOS vs. SOI, the differences between fully depleted and partially depleted SOI, and the FD-SOI ecosystem. [youtube vid=8ZhfJLkImlk] » read more

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