tag: Codasip

Selecting The Right RISC-V Core
By Brian Bailey - 16 Jan, 2023 - Comments: 0

With an increasing number of companies interested in devices based on the RISC-V ISA, and a growing number of cores, accelerators, and infrastructure components being made available, either commercially or in open-source form, end users face an increasingly difficult challenge of ensuring they make the best choices. Each user likely will have a set of needs and concerns that almost equals th... » read more

How Secure Are RISC-V Chips?
By Jeff Goldman - 05 Jan, 2023 - Comments: 3

When the Meltdown and Spectre vulnerabilities were first uncovered in 2018, they heralded an industry-wide shift in perspective regarding processor security. As the IBM X-Force Threat Intelligence Index put it the following year, "2018 ushered in a new era of hardware security challenges that forced enterprises and the security community to rethink the way they approach hardware security." R... » read more

Blog Review: Jan. 4
By Jesse Allen - 04 Jan, 2023 - Comments: 0

Siemens EDA's Harry Foster investigates the percentage of total IC/ASIC project time spent in verification and increasing engineering headcount, particularly growing demand for verification engineers. Synopsys' Stelios Diamantidis argues that retargeting older chips using AI offers a way to move chip designs between nodes and absorb the market’s excess capacity. Cadence's Paul McLellan ... » read more

RISC-V Pushes Into The Mainstream
By Marie C. Baca and Ed Sperling - 21 Dec, 2022 - Comments: 1

RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators and extra processing cores to security applications. These changes are subtle but significant. They point to a growing acceptance that chips or chiplets based on an open-source instruction set ar... » read more

Extending RISC-V Processors In The Field With Codasip Studio & Menta eFPGA
By Codasip - 21 Dec, 2022 - Comments: 0

RISC-V is an open specification that allows an infinite number of implementations. But RISC-V goes beyond that and encourages processor architects to add new instructions to accelerate certain algorithms or application domains, for example DSP, AI/ML, and others, while keeping the base instruction set stable. The new instructions may help with the performance, code size, power consumption, or d... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Dec, 2022 - Comments: 0

Power always has been a function of cost. The more power required, the more it costs to run a device, both in dollars and carbon footprint. This makes the breakthrough in fusion ignition at Lawrence Livermore National Laboratory all the more noteworthy, and one that could have significant implications for the future of computing, from data centers to rechargeable batteries in automobiles, robot... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Dec, 2022 - Comments: 0

Tools, IP, design Codasip launched a new organization within the company to support the development and commercialization of technical innovations in key applications including security, functional safety, and AI/ML. "As semiconductor scaling is showing its limits, there is an obvious need for new ways of thinking. We will be working with universities, research institutes and strategic partner... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 02 Dec, 2022 - Comments: 0

Automotive, Mobility The U.S. space agency NASA entered a $57.2 million contract with ICON to develop technology to build roads on the moon. ICON, a Texas-based 3D printing construction company, has been working with NASA and the U.S. Air Force on construction technologies that can use local materials to build infrastructure on Mars. NASA is working on advanced 3D printing construction systems... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 02 Dec, 2022 - Comments: 0

Tools and IP Renesas released a family of configurable clock generators with an internal crystal oscillator for PCIe and networking applications in high-end computing, wired infrastructure and data center equipment. “Timing needs can vary greatly between different applications and equipment, and often change during a product design cycle,” said Zaher Baidas, Vice President of the Timing Pr... » read more

Being A Design Verification Engineer Is Fun And Rewarding
By Lauranne Choquin - 22 Nov, 2022 - Comments: 0

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF encourages young people to study electronics and pursue careers in this sector, and on the other hand Codasip is very keen to help prepare the engineers who will solve tomorrow’s technology chall... » read more

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