RISC-V Pushes Into The Mainstream

Open-source processor cores are beginning to show up in heterogeneous SoCs and packages.


RISC-V cores are beginning to show up in heterogeneous SoCs and packages, shifting from one-off standalone designs toward mainstream applications where they are used for everything from accelerators and extra processing cores to security applications.

These changes are subtle but significant. They point to a growing acceptance that chips or chiplets based on an open-source instruction set architecture can be combined with silicon-proven cores from Arm, Synopsys (ARC), and Cadence (Tensilica Xtensa), and others, to create a relatively inexpensive and flexible customization option. And while RISC-V has yet to make a dent in standalone applications, companies such as Ventana Micro Systems are testing the waters for high-performance computing chiplets based on RISC-V for use in data centers.

RISC-V is unlikely to replace existing chip architectures anytime soon, but it certainly is commanding significant attention from hardware design community as it shifts from monolithic, one-vendor SoCs to heterogeneous, multi-chip advanced packaging. According to a recent Semico Research report, RISC-V IP is expected to grow at a 34.9% compound annual growth rate through 2027, compared to 9% growth for semiconductor IP.

There also are more than 3,180 RISC-V members in 70 countries, including 94 chip companies and 4 systems companies, according to RISC-V International. And with increasing pressure by government agencies to cut development costs and time, this is a market that clearly bears watching.

“This is looking very much like the ASIC model again,” said Sailesh Chittipeddi, executive vice president at Renesas Electronics. “But it’s no longer CPUs doing X, Y and Z functions for every workload, where there’s no overhead associated with it. Instead, there are all these companies going more verticalized to drive the solutions they need, whether that includes AI or some other things at the system level. This is why we’re seeing more CAD companies increasingly getting into system-level support and system-level design. And now you can get into each domain with more depth. More broadly, we’re finding systemic change occurring in the industry, with a move to providing solutions.”

RISC-V is emerging as an integral component in these heterogeneous solutions, and it is gaining traction for two main reasons. First, the open-source ISA allows it to be customized relatively simply, although for critical applications it still needs to be verified and tested using commercial EDA tools. Second, there are no royalties to pay once a design is completed, so for design teams with experienced processor engineers, RISC-V cores can be used to create customer- or application-specific designs without royalties.

Put simply, while there is one standard ISA, there are many possible implementations. “This is similar to Ethernet,” said Calista Redmond, CEO of the RISC-V Foundation. “There’s a standard, but there isn’t just one provider. What’s different is that RISC-V uses a modular approach. There is a base set of 47 instructions, and you add whatever extensions you need for different workloads. There’s also an extensive roadmap with different pieces in flight across 81 different working groups, which will be ratified and verified to meet security and safety standards.

The emphasis is on experienced engineering skills, though. Unlike an Arm core, for example, integrating RISC-V is not simple. Any RISC-V implementation needs to be fully characterized in context of use cases, end applications, what other components are within physical proximity, and how any of these components might impact the others. Connectivity, and the potential impact of that connectivity on other components, needs to be well understood and fully characterized under all known or expected conditions.

“At any given minute, you solve it the best you can for the chip that you’re working on right now,” said Rob Aitken, a Synopsys fellow. “And next time, you’ll have new CPUs with updated bandwidth to the external world, and maybe in a situation where everyone is starting to adopt UCIe. But you still have to go back to your overall chip or system architecture and determine what it is you’re trying to accomplish. You have some kind of compute system, some memory someplace, and different kinds of GPUs or accelerators added on. Then there’s the issue of how to make all of these colorful boxes in PowerPoint talk to each other, because at some point when you actually connect them together you may find this massive bottleneck that you have to figure out how to work around.”

Going heterogeneous
This is the challenge with heterogeneous designs, because not all of the blocks in an SoC, or chips/chiplets in an advanced package, were developed by the same engineering team. In many cases, they weren’t even developed in the same country. From an integration standpoint, the more components, the more complicated all of this becomes.

“One of the things that surprises people with the move to RISC-V is the freedom to innovate,” Simon Davidmann, president and CEO at Imperas Software. “We’ve got customers spending a lot of time on the network on chip savings. It’s all about how the chips talk to each other, what the network looks like, what the communication looks like. They have to validate and verify all of that, not only from a functionality point of view, but also from a performance point of view. We’re all on the same core but what’s different is the interconnection and how things communicate. RISC-V enables you to buy a core, configure it up, put down a thousand of them or a hundred of them, add vector engines, and then differentiate yourself with the network you’ve got and the software that’s on it.”

Others agree. “In the MCU world, you had all these companies that were doing the proprietary course, where you had the hardware and the software to give to the customer — the complete solution,” said Renesas’ Chittipeddi. “Then along came Arm, which created an environment where we had a flexible software package and Arm cores. Now there’s RISC-V. We caught this wave a little ahead of other companies, so when people were doing test chips we were launching products optimized for motor control applications. This year we had RISC-V optimized for voice applications. We can extend that concept right into other areas, too. The transformation that’s occurred on the MCU side and the MPU side has been significant, and RISC-V helped our automotive business to follow suit in a hurry.”

But while the advantages of RISC-V are becoming clearer, so too are the potential issues. Davidmann said quality and verification are enormous challenges for the RISC-V community, who generally cannot afford the same number of verification cycles as some of the larger processor companies. “We have to work together and collaborate to build the application ecosystem, because the quality of the cores is going to be a big challenge going forward,” he said.

Security is one of the growth areas within the ecosystem, both for developing tools and crypto cores, and for security of the chips themselves.

Rupert Baines, chief marketing officer at Codasip, believes chips that incorporate RISC-V have a clear advantage with regard to security, in part because it is based on open-source code. “There’s more emphasis on ‘sunlight is the best disinfectant,’ and so there’s more emphasis on viewing, checking, and seeing things,” he said. Ultimately, the security is dependent on how the architecture is implemented. “There are some systems out there that are going to be shockingly bad, and some that will be very, very good.”

Codasip recently acquired Cerberus Security Labs. Baines says Codasip is in the process of integrating Cerberus’ IP into Codasip products so customers can quickly create secure RISC-V processor designs.

RISC-V also serves as a customizable core for security solutions. Rambus, for example, developed a programmable root-of-trust anti-tamper core several years ago for government and military applications, that includes AES, RSA and ECC cryptographic accelerator cores and a true random number generator.

Riscure likewise developed specialized simulators to simulate security properties using RISC-V. “It shows the efficacy of hardware versus software countermeasures in a chip, and how hardware countermeasures can actually amplify the effectiveness of software countermeasures 10-fold,” said Maarten Bron, managing director of Riscure.

Next steps
What becomes apparent with RISC-V is that the whole ecosystem is evolving quickly. EDA vendors are racing to position their tools around RISC-V.

Case in point: Siemens EDA introduced a debugging tool based on the RISC-V working group standard, which is now in its second revision. “A lot of designs are not just RISC-V,” said Peter Shields, Tessent product manager at Siemens EDA. “Understanding program behavior in complex systems is a big challenge. It’s often very impractical to halt the core to debug the software. And that’s especially true in the context of real-time systems, where the nature of the systems does not wait when the core is halted. So what’s required is a non-intrusive way of observing program behavior at full speed. That enables you to see exactly how the software executes within the system and how it’s responding to a real-time event. Processor trace provides you with that ability to capture the sequence of executed instructions absolutely without halting the core.”

Other challenges have less to do with RISC-V than they do with the realities of working with smaller nodes. “As we move to smaller nodes, there are all these scaling issues and challenges,” said Davidmann. “It’s the physical mechanics of building this stuff and putting it together on the devices. We just started collaborating with some other companies on the SoC level, and if we get to the system level, it’s a long, slow process.”

Pushing into the data center and automotive applications will create even greater pressure to boost reliability of RISC-V designs. Researchers at the Universities of Bologna and Modena in Italy, and ETH Zurich, developed an open-source RISC-V-based SoC that is capable of running Linux using ultra low power. Researchers from the Barcelona Supercomputing Center in Spain also recently introduced a vector processing acceleration engine that integrates a RISC-V vector extension.

How well such projects fare against existing processors remains to be seen, but the move speaks to the growth and ambitions of RISC-V ecosystem.

Though RISC-V is unlikely to replace existing chip architectures soon, the growth of RISC-V cores in heterogenous SoCs and packages demonstrates that this open-source instruction set architecture is becoming increasingly mainstream. Among RISC-V’s advantages are the ability to customize and re-customize, and the fact that there are no royalties to pay once a design is completed. Moreover, it could provide an advantage for security thanks to the sheer number of companies and engineers collaborating on open-source code.

At the same time, RISC-V integration is not simple, and more applications are needed to manage core quality and verification. This rapidly-evolving ecosystem is sure to exhibit new advantages and challenges as it matures.

Efficient Trace In RISC-V
How to work with the new RISC-V debug standard.
RISC-V Knowledge Center


Dan Ganousis says:

“No royalties” has nothing to do with RISC-V …it’s a very common misconception. Yes, there is no charge/fee for an architectural license – unlike Arm where that license can cost 7 or 8 digits. Royalties however are being charged by some RISC-V vendors – like Arm, not so much for MCUs but definitely for applications processor IP.

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