Week In Review: Design, Low Power

Tools and IP

Renesas released a family of configurable clock generators with an internal crystal oscillator for PCIe and networking applications in high-end computing, wired infrastructure and data center equipment. “Timing needs can vary greatly between different applications and equipment, and often change during a product design cycle,” said Zaher Baidas, Vice President of the Timing Products Division at Renesas. “VersaClock 7 gives our customers the flexibility to configure multiple design parameters while offering the best value available for their particular performance requirements.” The company also said it was named “Outstanding Strategic Partner” by BYD Auto.

Complex designs and choices early in the design flow force EDA companies to rethink the virtual prototype. Read more here.

Cadence, UMC, and Gear Radio announced a successful tapeout of a low noise amplifier IC on the first pass using UMC’s 28HPC+ process technology and Cadence’s Virtuoso RF solution.

There’s no consensus on whether or not Universal Chiplet Interconnect Express (UCIe) will be able to join together multi-vendor chiplets in a single plug-and-play interface.

Imperas said Andes Technology certified Imperas reference models for the complete range of Andes processor IPs with Andes Custom Extension support and the new AndesCore N25F-SE targeted at functional safety applications. “Flexibility alone is insufficient for modern design flows as users depend on the established EDA tools and environments,” said Imperas CEO Simon Davidmann. “The Imperas reference models cover the entire range of Andes cores and offers a frictionless path for users to explore the new design freedoms offered by the flexibility of RISC-V supported in all the major EDA environments.”

Fully realizing the benefits of digital twins requires tying the approach together with system deployment.

Codasip said it is collaborating with Intel on the expansion of the Intel Pathfinder for RISC-V to include an increased focus on education. “The addition of Intel’s FPGA platforms into Codasip’s computer architecture project-based assignments will further boost our three University Program Pillars; preparing the next generation of researchers, training the next generation of engineers, and developing solutions to solve tomorrow’s technological challenges,” said Keith Graham, Codasip’s vice president of University and Customer Experience Program.

Researchers at Oxford University published a paper about how to extend the C programming language.

5G and 6G

Keysight launched several products aimed at improving quality of service in public and private 5G networks using automated remote monitoring. The products include the Nemo Industry Probe and Nemo Active Probe. Matti Passoja, Head of Nemo Wireless Solutions at Keysight, said: “Keysight’s new Industry 4.0 compliant active monitoring solution offers enhanced visibility into the state of a 5G private network from the perspective of the user equipment (UE). These new capabilities enable private 5G network operators to maintain continuous mission-critical levels of cellular connectivity in harsh indoor environments.” Keysight also said MediaTek used Keysight’s 5G Network Emulation Solutions to establish connectivity to its 5G chips using the 3GPP 5G Release 17 (Rel-17) and the 5G reduced capability (RedCap) specifications. Furthermore, Keysight introduced a new solar array simulator product for satellite power systems.

Quantum computing

A team of researchers used quantum computers to essentially “traverse a wormhole,” sending qubits from one entangled particle system to another in a model of gravity. The researchers used the Sycamore 53-qubit quantum processor.

McKinsey predicted that less than half of all quantum computing jobs will be filled by 2025 unless significant interventions take place.

General-purpose quantum computers don’t yet exist, but there are already questions about whether existing EDA tools will be sufficient for quantum designs. Read more here.

Financial Results

Synopsys reported earnings for the fourth quarter and fiscal year 2022. Fourth quarter revenue increased about 12% year-over-year to $1.28 billion. Revenue for the fiscal year increased more than 20% to $5.08 billion. Aart de Geus, the company’s chairman and CEO, said Synopsys targets 14-15% revenue growth, continued non-GAAP operating margin expansion, and approximately 16% non-GAAP earnings per share growth for fiscal year 2023. The company also said it won six partner of the year awards at the TSMC 2022 OIP Ecosystem Forum.

Upcoming Events

Dec. 6-Dec. 7, DVCon Europe 2022, Munich, Germany

Dec. 6, Ansys Ideas Digital Forum, virtual

Dec. 13-14, RISC-V Summit, San Jose, CA

Dec. 15, Club Formal India: The Forum For Formal Verification Users, Bengalruru, India

Find more events here.

In Case You Missed It

Check out the new Systems & Design newsletter as well as the Low Power, High Performance newsletter for these highlights and more:

• Is UCIe really universal?
• EDA tools for quantum chips
• Taking power much more seriously
• Solving thermal coupling issues in complex chips

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