tag: Coventor

The Future Of FinFETs At 5nm And Beyond
By Assawer Soussou - 05 Mar, 2021 - Comments: 0

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to finFET platforms, controlling RC parasitics and achieving higher transistor performance at technology nodes of 5nm and beyond becomes challenging. In collaboration with Imec, we recently used SEMulator3D virtual fabrication to explore an end-to-end solution to better underst... » read more

Evaluation Of The Impact Of Source Drain epi Implementation On Logic Performance Using Combined Process And Circuit Simulation
By Coventor - 17 Feb, 2021 - Comments: 0

In this paper, we explore an end-to-end solution using SEMulator3D to address the need to include process variation effects in circuit simulation. For the first time, we couple SEMulator3D with BSIM compact modeling to evaluate process variation impacts on circuit performance. The process integration goal of the study was to optimize contacts and spacer thickness of advanced-node FinFETs in ter... » read more

New Transistor Structures At 3nm/2nm
By Mark LaPedus - 25 Jan, 2021 - Comments: 12

Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect trans... » read more

An Introduction To Virtual Semiconductor Process Evaluation
By Jeonghoon (James) Kim - 21 Jan, 2021 - Comments: 0

Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps. Unfortunately, many process engineering problems cannot be solved with a brute force, step by step approach to understand every cause-and-effect relationship. There are simply too many process recipe variables that can be modified to make a brute-force... » read more

Process Window Optimization Of DRAM By Virtual Fabrication
By Daebin Yim - 21 Dec, 2020 - Comments: 0

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges. Industrial focus has shifted from the scaling of predictable unit processes in 2D structures to the more challenging full integration of complex 3D structures. Conventional 2D layout DRC, offline wafer metrology, and offline electrical measurements are no longer sufficient... » read more

Variation Threat In Advanced Nodes, Packages Grows
By Ed Sperling - 21 Dec, 2020 - Comments: 0

Variation is becoming a much bigger and more complex problem for chipmakers as they push to the next process nodes or into increasingly dense advanced packages, raising concerns about the functionality and reliability of individual devices, and even entire systems. In the past, almost all concerns about variation focused on the manufacturing process. What printed on a piece of silicon didn't... » read more

3D NAND’s Vertical Scaling Race
By Mark LaPedus - 17 Dec, 2020 - Comments: 1

3D NAND suppliers are accelerating their efforts to move to the next technology nodes in a race against growing competition, but all of these vendors are facing an assortment of new business, manufacturing, and cost challenges. Two suppliers, Micron and SK Hynix, recently leapfrogged the competition and have taken the scaling race lead in 3D NAND. But Samsung and the Kioxia-Western Digital (... » read more

Process Variation Analysis of Device Performance Using Virtual Fabrication
By Coventor - 16 Dec, 2020 - Comments: 0

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

Accelerating Dry Etch Processes During Feature Dependent Etch
By Timothy Yang - 23 Nov, 2020 - Comments: 0

In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (figure 1). This has an impact on etch results, since the etch rate at any point on the wafer will vary depending on the solid angle visible to the bulk chamber and the ion flux for that angular range. These non-uniform and feature dependent e... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 20 Nov, 2020 - Comments: 0

Fab tools PDF Solutions has entered into a definitive agreement to acquire Cimetrix. Under the terms, PDF will pay a cash amount of $35.0 million, net of cash on Cimetrix’s balance sheet as of closing, and subject to other closing adjustments. With the move, PDF will expand into new markets. Cimetrix is a provider of equipment connectivity products for smart manufacturing and Industry 4.0... » read more

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