tag: Coventor

Blog Review: May 12
By Jesse Allen - 12 May, 2021 - Comments: 0

Cadence's Claire Ying points to major changes in PCIe 6.0 as PAM4 signaling replaces NRZ to help double bandwidth, Forward Error Correction helps maintain data integrity, and various improvements are made to power consumption. Synopsys' Samantha Beaumont argues that automotive sensors are a major potential attack point and addresses some of the key areas of sensor vulnerability and the chall... » read more

Improving Your Understanding Of Advanced Inertial MEMS Design
By Chris Welham - 27 Apr, 2021 - Comments: 0

Micro-electrical-mechanical systems (MEMS) based inertial sensors are used measure acceleration and rotation rate. These sensors are integrated into units to measure motion, direction, acceleration or position, and can be found in a wide range of applications including smart phones, consumer electronics, medical devices, transportation systems, oil/gas exploration, military, aeronautical and sp... » read more

SVT (Six Stacked Vertical Transistors) SRAM Cell Architecture Introduction: Design And Process Challenges Assessment
By Coventor - 14 Apr, 2021 - Comments: 0

This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual fabrication technology was used to identify different process integration schemes to enable the fabrication of this architecture with a competitive XY footprint at an advanced logic node: a unit cell ... » read more

Overcoming Challenges In Next-Generation SRAM Cell Architectures
By Benjamin Vincent - 18 Mar, 2021 - Comments: 0

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to each other in order to perform logic storage and other functions. The size of the 6T (6 Transistors) SRAM cell has shrunk steadily over the past decades, thanks to Moore’s Law and the size reduction of t... » read more

Chasing After Carbon Nanotube FETs
By Mark LaPedus - 18 Mar, 2021 - Comments: 6

Carbon nanotube transistors are finally making progress for potential use in advanced logic chips after nearly a quarter century in R&D. The question now is whether they will move out of the lab and into the fab. Several government agencies, companies, foundries, and universities over the years have been developing, and are now making advancements with carbon nanotube field-effect transi... » read more

SVT: Six Stacked Vertical Transistors
By Coventor - 17 Mar, 2021 - Comments: 0

This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual fabrication technology was used to identify different process integration schemes to enable the fabrication of this architecture with a competitive XY footprint at an advanced logic node: a unit cell ... » read more

The Future Of FinFETs At 5nm And Beyond
By Assawer Soussou - 05 Mar, 2021 - Comments: 0

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to finFET platforms, controlling RC parasitics and achieving higher transistor performance at technology nodes of 5nm and beyond becomes challenging. In collaboration with Imec, we recently used SEMulator3D virtual fabrication to explore an end-to-end solution to better underst... » read more

Evaluation Of The Impact Of Source Drain epi Implementation On Logic Performance Using Combined Process And Circuit Simulation
By Coventor - 17 Feb, 2021 - Comments: 0

In this paper, we explore an end-to-end solution using SEMulator3D to address the need to include process variation effects in circuit simulation. For the first time, we couple SEMulator3D with BSIM compact modeling to evaluate process variation impacts on circuit performance. The process integration goal of the study was to optimize contacts and spacer thickness of advanced-node FinFETs in ter... » read more

New Transistor Structures At 3nm/2nm
By Mark LaPedus - 25 Jan, 2021 - Comments: 12

Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect trans... » read more

An Introduction To Virtual Semiconductor Process Evaluation
By Jeonghoon (James) Kim - 21 Jan, 2021 - Comments: 0

Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps. Unfortunately, many process engineering problems cannot be solved with a brute force, step by step approach to understand every cause-and-effect relationship. There are simply too many process recipe variables that can be modified to make a brute-force... » read more

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