tag: Coventor

Backside Power Delivery as a Scaling Knob for Future Systems
By Coventor - 14 Aug, 2019 - Comments: 0

Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO explorat... » read more

Process Window Optimization
By Ed Sperling - 07 Aug, 2019 - Comments: 0

David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling. » read more

Node Within A Node
By Ed Sperling - 24 Jul, 2019 - Comments: 0

Enough margin exists in manufacturing processes to carve out the equivalent of a full node of scaling, but shrinking that margin will require a collective push across the entire semiconductor manufacturing supply chain. Margin is built into manufacturing at various stages to ensure that chips are manufacturable and yield sufficiently. It can include everything from variation in how lines are... » read more

Process Modeling Exploration for 8 nm Half-Pitch Interconnects
By Coventor - 17 Jul, 2019 - Comments: 0

In this paper, we simulate eSADP, eSAQP and iSAOP patterning options to enable fabrication of 8 nm Half-Pitch (HP) interconnects. We investigate the impact of process variations and patterning sensitivities on pitch walking and resistance performance. The overall yield is also calculated for eight line CDs as well as M2-via-M1 via segment resistance and compared for all options. Process sensiti... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 12 Jul, 2019 - Comments: 0

Semi takeover targets Semiconductor M&A activity is heating up again. So who is next? “Within our coverage universe, we believe AMBA (Ambarella) and SLAB (Silicon Labs) represent the most likely targets moving forward,” according to KeyBanc in a research note. KeyBanc also listed some other “M&A Combinations That Could Make Sense.” Some of these combos make sense, while othe... » read more

Manufacturing Bits: July 10
By Mark LaPedus - 10 Jul, 2019 - Comments: 0

Semicon West It’s Semicon West time again. Here’s the first wave of announcements at the event: Applied Materials has unveiled a pair of tools aimed at accelerating the industry adoption for new memories. First, Applied rolled out the Endura Clover MRAM PVD system. The system is an integrated platform for MRAM devices. Second, the company introduced the Endura Impulse PVD platform for P... » read more

Controlling Variability Using Semiconductor Process Window Optimization
By Benjamin Vincent - 01 Jul, 2019 - Comments: 0

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. These specifications include critical dimensions, electrical performance requirements, and other device characteristics. Pre-production or ramp-up production Si wa... » read more

Advanced Process Control
By Ed Sperling - 20 Jun, 2019 - Comments: 0

David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures. » read more

New Advancements in Using Statistical Models as Part of a Standard MEMS Design Flow
By Coventor - 19 Jun, 2019 - Comments: 0

This paper presents the benefits of using statistical models during MEMS design, through the virtual reproduction of a test structure for measuring a beam’s pull-in voltage. This electrical measurement is used as a functional indicator of the process quality for manufactured wafers. Statistical variations of process parameters (material properties, silicon thickness, sidewall angle and edge s... » read more

Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing
By Pradeep Nanja - 23 May, 2019 - Comments: 0

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy