tag: Coventor

Effects of a Random Process Variation on the Transfer Characteristics of a Fundamental Photonic Integrated Circuit Component
By Coventor - 24 Jan, 2019 - Comments: 0

Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

N7 FinFET Self-Aligned Quadruple Patterning Modeling
By Coventor - 14 Dec, 2018 - Comments: 0

Authors: Sylvain Baudot, Sofiane Guissi, Alexey P. Milenin, Joseph Ervin, Tom Schram (IMEC and COVENTOR) In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning proces... » read more

Some Chipmakers Sidestep Scaling, Others Hedge
By Ed Sperling - 15 Nov, 2018 - Comments: 0

The rising cost of developing chips at 7nm coupled with the reduced benefits of scaling have pried open the floodgates for a variety of options involving new materials, architectures and packaging that either were ignored or not fully developed in the past. Some of these approaches are closely tied to new markets, such as assisted and autonomous vehicles, robotics and 5G. Others involve new ... » read more

CMOS Area Scaling And The Need For High Aspect Ratio Vias
By Coventor - 26 Oct, 2018 - Comments: 0

Resolving internal routing congestion will be essential to enable CMOS area scaling to the N5 node and beyond. The solution will require new design maneuvers in place and route (PnR), as well as patterning innovations. In this work, we present inter-layer high aspect ratio vias or ‘SuperVia’ (SV) as one technology element that could enable track height scaling to 4.5T at aggressive N5 dime... » read more

3D NAND: Challenges Beyond 96-Layer Memory Arrays
By Steve Shih-Wei Wang - 24 Oct, 2018 - Comments: 0

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working ... » read more

Carmakers To Chipmakers: Where’s The Data?
By Ed Sperling And Susan Rambo - 24 Oct, 2018 - Comments: 0

The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Blog Review: Oct. 24
By Jesse Allen - 24 Oct, 2018 - Comments: 0

Arm's Shidhartha Das digs into Power Delivery Networks with a look at how the specific roles of different components work to provide smooth supply conditions. In a video, VLSI Research's Dan Hutcheson chats with D2S CEO Aki Fujimura about the state of the photomask market, EUV optimism, and the most interesting findings from this year's eBeam Initiative survey. Synopsys' Prasad Subudhi K.... » read more

Lab-To-Fab Testing
By Ed Sperling - 08 Oct, 2018 - Comments: 0

Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm
By Ed Sperling - 20 Sep, 2018 - Comments: 1

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

Using AI In Chip Manufacturing
By Ed Sperling - 22 Aug, 2018 - Comments: 0

David Fried, CTO at Coventor, a Lam Research Company, sat down with Semiconductor Engineering to talk about how AI and Big Data techniques will be used to improve yield and quality in chip manufacturing. What follows are excerpts of that conversation. SE: We used to think about manufacturing data in terms of outliers, but as tolerances become tighter at each new node that data may need to b... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy