Pattern Dependence Process Modeling


First order process modeling can help tremendously with process setup and integration challenges that occur in a semiconductor fabrication flow, by visualizing process variation problems “virtually” prior to actual fabrication. In some instances, a deeper level of complexity needs to be added to the process model to capture the effects of variation in the process. Specific examples inclu... » read more

Virtual Fabrication For MEMS Process Development


MEMS fabrication and design are closely coupled, such that design changes could significantly alter the process flow and vice versa. For instance, setting device parameters such as drive capacitance, deflection distance, or proof mass size directly affects the choice of film thickness, etch rate, sidewall profile and so forth. Typically, this requires multiple iterations of the MEMS design/proc... » read more

Atomic Layer Etch Heats Up


The atomic layer etch (ALE) market is starting to heat up as chipmakers push to 10nm and beyond. ALE is a promising next-generation etch technology that has been in R&D for the last several years, but until now there has been little or no need to use it. Unlike conventional etch tools, which remove materials on a continuous basis, ALE promises to selectively and precisely remove targete... » read more

Blog Review: June 29


Ansys' Justin Nescott checks out the world's first electric highway for trucking in this week's top five tech picks. Plus, some cool houses, Boston Dynamics' giraffe-bot, and a drum kit in a backpack. Applied's Matt Cogorno takes a look at the challenges facing etch methods as devices keep getting smaller. Synopsys' Apoorva Mathur digs into the energy efficient aspects of the MIPI M-PHY a... » read more

Interconnect Challenges Rising


Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

IMEC Partner Technical Week Review


In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every six months to present scientific results to their partners. During this week, a number of specialists from IMEC's many partner companies also discuss their progress in areas related to IM... » read more

Next Challenge: Contact Resistance


In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact. Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or conta... » read more

Back-End-of-Line (BEOL) Metallization


Physical Vapor Deposition (PVD) for Back-End-of-Line (BEOL) metallization is being pushed to the limits at the 16-nanometer (nm) technology node and beyond. Extending PVD for metal liner and barrier seed deposition is forcing the process into a narrow window that must be characterized prior to manufacturing introduction. Furthermore, understanding the liner dependency on the trench and via etch... » read more

The Week In Review: Manufacturing


MEMS manufacturing A*STAR’s Institute of Microelectronics (IME) in Singapore has launched its third consortium to develop MEMS technologies. This would allow MEMS sensor devices to achieve better performance, higher power efficiency and a smaller form factor. The MEMS Consortium III consists of the following companies: Applied Materials, Coventor, Delta Electronics, GlobalFoundries, InvenS... » read more

DAC Day Four: Excitement And Risk


One thing that was new to DAC this year, was an art exhibit. These were pieces of artwork related to our industry, such as chip plots, or more abstract ideas based on design data or analyses. They received many more entrants than their wildest dreams and had to choose a winner from over 80 pieces, but the grand prize was won by a 3D model of a finFET by David Freid of Coventor. This piece was ... » read more

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