tag: Coventor

Blog Review: Jan. 18
By Jesse Allen - 18 Jan, 2023 - Comments: 0

Synopsys' Dana Neustadter, Sara Zafar Jafarzadeh, and Ruud Derwig argue that we are already at an inflection point for post-quantum security because devices and infrastructure systems with longer life cycles or communicating data that must be kept confidential for an extended period need to have a path towards quantum-safe solutions. Siemens EDA's Harry Foster looks at trends in adoption of ... » read more

Metrology Options Increase As Device Needs Shift
By Laura Peters - 10 Jan, 2023 - Comments: 1

Semiconductor fabs are taking an ‘all hands on deck’ approach to solving tough metrology and yield management challenges, combining tools, processes, and other technologies as the chip industry transitions to nanosheet transistors on the front end and heterogenous integration on the back end. Optical and e-beam tools are being extended, while X-ray inspection is being added on a case-by-... » read more

Blog Review: Jan. 4
By Jesse Allen - 04 Jan, 2023 - Comments: 0

Siemens EDA's Harry Foster investigates the percentage of total IC/ASIC project time spent in verification and increasing engineering headcount, particularly growing demand for verification engineers. Synopsys' Stelios Diamantidis argues that retargeting older chips using AI offers a way to move chip designs between nodes and absorb the market’s excess capacity. Cadence's Paul McLellan ... » read more

How Far Will Copper Interconnects Scale?
By Laura Peters - 15 Dec, 2022 - Comments: 0

As leading chipmakers continue to scale finFETs — and soon nanosheet transistors — to ever-tighter pitches, the smallest metal lines eventually will become untenable using copper with its liner and barrier metals. What comes next, and when, is still to be determined. There are multiple options being explored, each with its own set of tradeoffs. Ever since IBM introduced the industry to c... » read more

Automotive MEMS Accelerometer Design Verification: A Real Life Example
By Arnaud Parent - 15 Dec, 2022 - Comments: 0

Standard Finite Element (FE) models, especially those that incorporate multiple physical domains, consist of detailed representations of a device that include a large number of Degrees of Freedom (DoF). The Degrees of Freedom in a design are the number of independent variables or parameters needed to describe the motion or state of the device. Generally, the larger the number of Degrees of Free... » read more

Pathfinding By Process Window Modeling: Advanced DRAM Capacitor Patterning Process Window Evaluation Using Virtual Fabrication
By Coventor - 14 Dec, 2022 - Comments: 0

In advanced DRAM, capacitors with closely packed patterning are designed to increase cell density. Thus, advanced patterning schemes, such as multiple litho-etch, SADP and SAQP processes may be needed. In this paper, we systematically evaluate a DRAM capacitor hole formation process that includes SADP and SAQP patterning, using virtual fabrication and statistical analysis in SEMulator3D. The pu... » read more

Blog Review: Dec. 7
By Jesse Allen - 07 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at the continual maturing of FPGA functional verification processes through increasing adoption of various simulation-based and formal verification techniques. Synopsys' Stewart Williams introduces the Scalable Open Architecture for Embedded Edge (SOAFEE) project and how it can make automotive software development, testing, virtual prototyping, and validation... » read more

Making Chips Yield Faster At Leading-Edge Nodes
By Ed Sperling - 30 Nov, 2022 - Comments: 0

Simulation for semiconductor manufacturing is heating up, particularly at the most advanced nodes where data needs to be analyzed in the context of factors such as variation and defectivity rates. Semiconductor Engineering sat down with David Fried, corporate vice president of computational products at Lam Research, to talk about what's behind Lam's recent acquisition of Esgee Technologies, ... » read more

Creating Airgaps To Reduce Parasitic Capacitance In FEOL
By Sumant Sarkar - 17 Nov, 2022 - Comments: 0

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the effective dielectric constant of the material layers between the gate and source/drain. This can be done by creating airgaps in the dielectric material at that location. This type of work has been do... » read more

Blog Review: Nov. 16
By Jesse Allen - 16 Nov, 2022 - Comments: 0

Siemens EDA's Jake Wiltgen explains the difference between transient and permanent faults when designing to the ISO 26262 standard, including where they come from and key ways to protect against them. Synopsys' Vikas Gautam points to how the economics of designing large SoCs is driving chiplet-based designs and the need for die-to-die standards such as UCIe, along with the key protocol verif... » read more

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