tag: Coventor

Blog Review: Nov. 9
By Jesse Allen - 09 Nov, 2022 - Comments: 0

Cadence's Claire Ying finds that the latest update to CXL, which introduced memory-centric fabric architectures and expanded capabilities for improving scale and optimizing resource utilization, could change how some of the world’s largest data centers and fastest supercomputers are built. Synopsys' Gervais Fong and Morten Christiansen examine the latest updates in the USB 80Gbps specifica... » read more

SiPs: The Best Things in Small Packages
By Laura Peters - 20 Oct, 2022 - Comments: 0

System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes. SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical p... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication
By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

Blog Review: Oct. 5
By Jesse Allen - 05 Oct, 2022 - Comments: 0

Arm's Andrew Pickard chats with Georgia Tech's Azad Naeemi and Da Eun Shim about an effort to evaluate the benefit of new interconnect materials and wire geometry and determine their impacts at the microprocessor level. Synopsys' Shekhar Kapoor shares highlights from a recent panel exploring the promises, challenges, and realities of 3D IC technology, including the potential of 3D nanosystem... » read more

Blog Review: Sept. 28
By Jesse Allen - 28 Sep, 2022 - Comments: 0

Cadence's Paul McLellan shares more highlights from the recent Hot Chips, including some very large chips and accelerators for AI and deep learning, new networks and switches, and mobile and edge processors. Synopsys' Marc Serughetti considers the different use cases for digital twins in automotive and how they can help determine the impact of software on verification, test, and validation a... » read more

How Does Line Edge Roughness (LER) Affect Semiconductor Performance At Advanced Nodes?
By Yu De Chen - 26 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line to line spacing, which introduces higher metal line resistance and line to line capacitance. This is demonstrated in figure 1, which displays a simulation of line resistance vs. line CD across different BEOL metals. Even without... » read more

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

A Study Of The Impact Of Line Edge Roughness On Metal Line Resistance Using Virtual Fabrication
By Coventor - 15 Sep, 2022 - Comments: 0

BEOL metal line RC delay has become a dominant factor limiting chip operation speeds at advanced nodes. This is because smaller metal line pitches require narrower line CD and line-to-line spacing, which introduces higher metal line resistance and line-to-line capacitance. A surface scattering effect is the root cause for the exponentially increased metal resistivity at smaller metal line pitch... » read more

Blog Review: Aug. 24
By Jesse Allen - 24 Aug, 2022 - Comments: 0

Synopsys' Manuel Mota presents an overview of some of the newest multi-chip module packaging types and their advantages and disadvantages for different kinds of applications, as well as the importance of die-to-die interfaces. Cadence's Steve Brown finds that innovative products require that electronics be analyzed in the context of the environment in which they run, making mechanical and el... » read more

Big Changes In Architectures, Transistors, Materials
By Ed Sperling - 18 Aug, 2022 - Comments: 0

Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

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