tag: Coventor

Automotive MEMS Accelerometer Design Verification: A Real Life Example
By Arnaud Parent - 15 Dec, 2022 - Comments: 0

Standard Finite Element (FE) models, especially those that incorporate multiple physical domains, consist of detailed representations of a device that include a large number of Degrees of Freedom (DoF). The Degrees of Freedom in a design are the number of independent variables or parameters needed to describe the motion or state of the device. Generally, the larger the number of Degrees of Free... » read more

Pathfinding By Process Window Modeling: Advanced DRAM Capacitor Patterning Process Window Evaluation Using Virtual Fabrication
By Coventor - 14 Dec, 2022 - Comments: 0

In advanced DRAM, capacitors with closely packed patterning are designed to increase cell density. Thus, advanced patterning schemes, such as multiple litho-etch, SADP and SAQP processes may be needed. In this paper, we systematically evaluate a DRAM capacitor hole formation process that includes SADP and SAQP patterning, using virtual fabrication and statistical analysis in SEMulator3D. The pu... » read more

Blog Review: Dec. 7
By Jesse Allen - 07 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at the continual maturing of FPGA functional verification processes through increasing adoption of various simulation-based and formal verification techniques. Synopsys' Stewart Williams introduces the Scalable Open Architecture for Embedded Edge (SOAFEE) project and how it can make automotive software development, testing, virtual prototyping, and validation... » read more

Making Chips Yield Faster At Leading-Edge Nodes
By Ed Sperling - 30 Nov, 2022 - Comments: 0

Simulation for semiconductor manufacturing is heating up, particularly at the most advanced nodes where data needs to be analyzed in the context of factors such as variation and defectivity rates. Semiconductor Engineering sat down with David Fried, corporate vice president of computational products at Lam Research, to talk about what's behind Lam's recent acquisition of Esgee Technologies, ... » read more

Creating Airgaps To Reduce Parasitic Capacitance In FEOL
By Sumant Sarkar - 17 Nov, 2022 - Comments: 0

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the effective dielectric constant of the material layers between the gate and source/drain. This can be done by creating airgaps in the dielectric material at that location. This type of work has been do... » read more

Blog Review: Nov. 16
By Jesse Allen - 16 Nov, 2022 - Comments: 0

Siemens EDA's Jake Wiltgen explains the difference between transient and permanent faults when designing to the ISO 26262 standard, including where they come from and key ways to protect against them. Synopsys' Vikas Gautam points to how the economics of designing large SoCs is driving chiplet-based designs and the need for die-to-die standards such as UCIe, along with the key protocol verif... » read more

Blog Review: Nov. 9
By Jesse Allen - 09 Nov, 2022 - Comments: 0

Cadence's Claire Ying finds that the latest update to CXL, which introduced memory-centric fabric architectures and expanded capabilities for improving scale and optimizing resource utilization, could change how some of the world’s largest data centers and fastest supercomputers are built. Synopsys' Gervais Fong and Morten Christiansen examine the latest updates in the USB 80Gbps specifica... » read more

SiPs: The Best Things in Small Packages
By Laura Peters - 20 Oct, 2022 - Comments: 0

System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes. SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical p... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication
By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

Blog Review: Oct. 5
By Jesse Allen - 05 Oct, 2022 - Comments: 0

Arm's Andrew Pickard chats with Georgia Tech's Azad Naeemi and Da Eun Shim about an effort to evaluate the benefit of new interconnect materials and wire geometry and determine their impacts at the microprocessor level. Synopsys' Shekhar Kapoor shares highlights from a recent panel exploring the promises, challenges, and realities of 3D IC technology, including the potential of 3D nanosystem... » read more

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