Software-Hardware Co-Design Becomes Real

By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Vector Runahead

By Technical Paper Link - 19 Aug, 2021 - Comments: 0

Abstract: "The memory wall places a significant limit on performance for many modern workloads. These applications feature complex chains of dependent, indirect memory accesses, which cannot be picked up by even the most advanced microarchitectural prefetchers. The result is that current out-of-order superscalar processors spend the majority of their time stalled. While it is possible to bui... » read more

Optimize Physical Verification Cost Of Ownership With Elastic CPU Management

By Synopsys - 07 Jul, 2021 - Comments: 0

For physical verification, advanced process technology nodes create implementation challenges. Design sizes have gotten larger and required rules from foundries have become more numerous in count (thousands) and more complex (hundreds of discrete steps). For these reasons, physical verification tools have been able to span these jobs not only across multiple CPUs on a single physical compute ho... » read more

CEO Outlook: More Data, More Integration, Same Deadlines

By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Tradeoffs To Improve Performance, Lower Power

By Ann Mutschler - 11 Mar, 2021 - Comments: 0

Generic chips are no longer acceptable in competitive markets, and the trend is growing as designs become increasingly heterogeneous and targeted to specific workloads and applications. From the edge to the cloud, including everything from vehicles, smartphones, to commercial and industrial machinery, the trend increasingly is on maximizing performance using the least amount of energy. This ... » read more

Von Neumann Is Struggling

By Brian Bailey - 18 Jan, 2021 - Comments: 5

In an era dominated by machine learning, the von Neumann architecture is struggling to stay relevant. The world has changed from being control-centric to one that is data-centric, pushing processor architectures to evolve. Venture money is flooding into domain-specific architectures (DSA), but traditional processors also are evolving. For many markets, they continue to provide an effective s... » read more

Powering The Edge: Driving Optimal Performance With Ethos-N77 Processor

By Arm - 09 Dec, 2020 - Comments: 0

Repurposing a CPU, GPU, or DSP is an easy way to add ML capabilities to an edge device. However, where responsiveness or power efficiency is critical, a dedicated Neural Processing Unit (NPU) may be the best solution. In this paper, we describe how the Arm Ethos-N77 NPU delivers optimal performance. Click here to immediately download the paper. » read more

Versal: The First Adaptive Compute Acceleration Platform (ACAP)

By Xilinx - 01 Dec, 2020 - Comments: 0

Recent technical challenges have forced the industry to explore options beyond the conventional “one size fits all” CPU scalar processing solution. Very large vector processing (DSP, GPU) solves some problems, but it runs into traditional scaling challenges due to inflexible, inefficient memory bandwidth usage. Traditional FPGA solutions provide programmable memory hierarchy, but the tradit... » read more

The Next Phase Of Computing

By Ed Sperling - 16 Nov, 2020 - Comments: 0

Apple's new M1 chip offers a glimpse of what's ahead, and not just from Apple. Being able to get 18 to 20 hours of battery life from a laptop computer moves the ball much farther down the field in semiconductor design. All of this is entirely dependent on the applications, of course. But what's important here is how much battery life and performance can be gained by designing hardware specif... » read more

Designs Beyond The Reticle Limit

By Brian Bailey - 12 Nov, 2020 - Comments: 0

Designs continue to grow in size and complexity, but today they are reaching both physical and economic challenges. These challenges are causing a reversal of the integration trend that has provided much of the performance and power gains over the past couple of decades. The industry, far from giving up, is exploring new ways to enable designs to go beyond the reticle size, which is around 8... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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Megafabs churning out the most advanced processors are not the only game in town.

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