High-Speed SerDes At 7nm

By Ed Sperling - 30 Jul, 2018 - Comments: 0

eSilicon’s David Axelrad discusses the challenges with 56Gbps and 112Gps SerDes, and why the switch from analog to digital is required for performance and low power. https://youtu.be/E-CU8TLvjjc » read more

IP Electromagnetic Crosstalk Requires Contextual Signoff

By Magdy Abadir - 16 Apr, 2018 - Comments: 0

By Magdy Abadir and Anand Raman Continuous advancement in technology scaling is enabling the emergence of high-performance application markets such as artificial intelligence, autonomous cars and 5G communication. These electronic systems operate at multi-GHz speed, while consuming the lowest amount of power possible leaving very little margin for error. Chips in these systems are highly in... » read more

Why Inductance Is Good for Area, Power and Performance

By Magdy Abadir - 12 Mar, 2018 - Comments: 0

By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

Tech Talk: 5/3nm Parasitics

By Ed Sperling - 22 Feb, 2018 - Comments: 0

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

Symptoms Of SoC Electromagnetic (EM) Crosstalk

By Anand Raman - 14 Feb, 2018 - Comments: 0

By Anand Raman and Magdy Abadir Have you ever had your silicon demonstrate unexpected behavior? Have you ever found unexplainable design failure or performance degradation? A number of issues could be the culprit - from overloaded signal nets, a noisy power grid, or increasing temperature - but one problem often overlooked is electromagnetic (EM) crosstalk. Electromagnetic (EM) crosstal... » read more

3D Neuromorphic Architectures

By Katherine Derbyshire - 11 Dec, 2017 - Comments: 1

Matrix multiplication is a critical operation in conventional neural networks. Each node of the network receives an input signal, multiplies it by some predetermined weight, and passes the result to the next layer of nodes. While the nature of the signal, the method used to determine the weights, and the desired result will all depend on the specific application, the computational task is simpl... » read more

Crosstalk Analysis At 7nm

By Magdy Abadir - 12 Oct, 2017 - Comments: 0

The increasing demand for electronic systems with increasing bandwidth and decreasing size puts more high-speed circuitry and high bandwidth channels in ever-closer proximity. The continuous increase in internal clock frequencies (e.g. 5 - 10 GHz) and the increase in data rates (e.g. >10Gbps) are fueling the emergence of electromagnetic (EM) crosstalk issues. Parasitic inductance and indu... » read more

Noise Issues At 10nm And Below

By Magdy Abadir - 14 Sep, 2017 - Comments: 0

Most of the conversations below 10nm have been about lithography, materials and design constraints. But as companies push to 7nm and beyond, they are faced with a host of new challenges, including how to deal with electromagnetic crosstalk. Electromagnetic crosstalk is unwanted interference caused by the electric and magnetic fields of one or more signals (aggressors) affecting another sign... » read more

Noise Killed My Chip

By Brian Bailey - 08 Sep, 2016 - Comments: 0

In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed. Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: crosstalk