Ready For Curvilinear: New Innovations For Resistance Extraction

By Siemens EDA - 29 Aug, 2024 - Comments: 0

The rapid evolution of semiconductor industry, fueled by the propagation of IOT applications, image sensors, photonics and MEMS applications and other emerging technologies dramatically increased the complexity of IC design. Designers often use unconventional structures to achieve the desired functionality and optimal performance. For example, image sensors use wide polygons in the layout and a... » read more

Single Vs. Multi-Patterning Advancements For EUV

By Gregory Haley - 20 Jun, 2024 - Comments: 0

As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

Opportunities Grow For GPU Acceleration

By Gregory Haley - 05 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the impact of GPU acceleration on mask design and production and other process technologies, with Aki Fujimura, CEO of D2S; Youping Zhang, head of ASML Brion; Yalin Xiong, senior vice president and general manager of the BBP and reticle products division at KLA; and Kostas Adam, vice president of engineering at Synopsys. W... » read more

Navigating The GPU Revolution

By Gregory Haley - 24 Apr, 2024 - Comments: 0

The Challenges Of Working With Photonics

By Karen Heyman - 01 Apr, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about where photonics is most useful — and most vulnerable — with James Pond, fellow at Ansys; Gilles Lamant, distinguished engineer at Cadence; and Mitch Heins, business development manager for photonic solutions at Synopsys. What follows are excerpts of that conversation. To view part one of this discussion, click here. ... » read more

The Next Chip Shortages?

By Ed Sperling - 15 Jun, 2023 - Comments: 0

The rollout of chiplets and heterogeneous designs could have unexpected implications on a global scale, creating a whole new round of chip shortages that will be much harder to fix. It's impossible to say for certain what will happen here in the wake of massive changes in chip design and a fluid and unpredictable geopolitical situation. The trade war between the United States and China began... » read more

Why Changes In Computing Are Driving Changes In Photomasks

By Ed Sperling - 18 Oct, 2022 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about massive improvements in computation based upon increased density on chips, and why printing Manhattan shapes on a photomask are no longer sufficient to print high-performance devices with predictable reliability every time. He explains why a discontinuity in EDA physical design has opened the door for printing curvilinear shap... » read more

Using GPUs In Semiconductor Manufacturing

By Ed Sperling - 25 Apr, 2022 - Comments: 0

Massive simulation and curvilinear shapes are forcing the photomask industry to rethink what types of chips work best. Aki Fujimura, CEO of D2S, talks about what happens when shapes printed on a mask are closer to what actually gets printed, how GPUs can be used to accelerate CPUs in single instruction/multiple data (SIMD) operations, and why pixel data is different from other data. » read more

The Benefits Of Curvilinear Shapes On Photomasks

By Jan Willis - 15 Mar, 2021 - Comments: 0

Do you have four minutes to hear why companies like Micron Technology think that curvilinear shapes on photomasks are an advantage? In a short video, Ezequiel Russell, Senior Director of Mask Technology at Micron Technology shows how curvilinear shapes can increase process windows for advanced memory as shown in figure 1. The video was part of a longer panel discussion with industry experts at ... » read more

Big Changes In Patterning

By Ed Sperling - 22 Feb, 2017 - Comments: 0

Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], sat down with Semiconductor Engineering to discuss patterning issues at 10nm and below, including mask alignment, the need for GPU acceleration, EUV's future impact on the total number of masks, and what the re-introduction of curvilinear shapes will mean for design. SE: Patterning issues are getting a lot of attention at 10nm and 7n... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?