Adapting To Broad Shifts Essential In 2022


Change creates opportunity, but not every company is able to respond quickly enough to take advantage of those opportunities. Others may respond too quickly, before they properly understand the implications. At the start of a typical year, optimism is in plentiful supply. Any positive trend is seen as continuing, and any negative is seen as turning around. Normally the later in the year that... » read more

Is UCIe Really Universal?


Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

CXL 3.0: From Expansion To Scaling


At the Flash Memory Summit in August, the CXL Consortium released the latest, and highly anticipated, version 3.0 of the Compute Express Link (CXL) specification. This new version of the specification builds on previous generations and introduces several compelling new features that promise to increase data center performance and scalability, while reducing the total cost of ownership (TCO). ... » read more

How Memory Design Optimizes System Performance


Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

Week In Review: Auto, Security, Pervasive Computing


The great EV ramp EV-related developments are everywhere. California’s move to ban sales of new internal-combustion vehicles by 2035, and the U.S. government’s sweeping embrace of clean-energy, are in lockstep with recent moves by the auto industry and related supply chains, as well as cutting-edge research. One of the big breakthroughs is the ability to charge an EV in 10 minutes witho... » read more

Week In Review: Design, Low Power


Quantum computing Baidu introduced a 10-qubit quantum computer called Qianshi and what it described as “the world's first all-platform quantum hardware-software integration solution that provides access to various quantum chips via mobile app, PC, and cloud.” The company said it has also completed the design of a 36-qubit quantum chip. Scientists said “levitating” nanoparticles co... » read more

Finding the Scope of CXL-Enabled Tiered Memory System in Production


This new technical paper titled "TPP: Transparent Page Placement for CXL-Enabled Tiered Memory" is presented by researchers at University of Michigan and Meta Inc. Abstract (partial) "We propose a novel OS-level application-transparent page placement mechanism (TPP) for efficient memory management. TPP employs a lightweight mechanism to identify and place hot and cold pages to appropriate... » read more

Compute Express Link (CXL): All You Need To Know


An in-depth look at Compute Express Link  (CXL) 2.0, an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) and machine learning (ML) applications. We discuss how CXL technology maintains memory c... » read more

Research Bits: July 18


CXL memory disaggregation Researchers from the Korea Advanced Institute of Science and Technology (KAIST) developed a Compute Express Link (CXL) solution for directly accessible, high-performance memory disaggregation that they say significantly improves performance compared to existing remote direct memory access (RDMA)-based memory disaggregation. RDMA enables a host to directly access an... » read more

What Future Processors Will Look Like


Mark Papermaster, CTO at AMD, sat down with Semiconductor Engineering to talk about architectural changes that are required as the benefits of scaling decrease, including chiplets, new standards for heterogeneous integration, and different types of memory. What follows are excerpts of that conversation. SE: What does a processor look like in five years? Is it a bunch of chips in a package? I... » read more

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