Measuring And Analyzing SoC Performance With Verdi Performance Analyzer

By Synopsys - 23 May, 2018 - Comments: 0

SoC performance is a key competitive advantage in the marketplace. The choice and configuration of SoC components—protocol IP and interconnects, is geared towards maximizing overall SoC performance. A case in point is the use of HBM (High Bandwidth Memory) technology and controllers. Currently in its third generation, HBM boasts high-performance while using less power in a substantially small... » read more

Optimizing Your DRC Debug Can Reap Big Productivity Gains

By Srinivas Velivala - 10 May, 2018 - Comments: 0

Debugging design violations found by design rule checking (DRC) has always taken a significant share of the time needed to get a design to tapeout. And debug time only increases as the number and complexity of DRC expands with each new process node. Any steps you can take to make your DRC debug process more efficient directly improves your productivity. One technique for minimizing debug tim... » read more

Digital Twins: Making The Vision Achievable

By Ansys - 09 May, 2018 - Comments: 0

Few business concepts are generating the buzz of digital twins — product replicas that can help target performance issues and allow for true predictive maintenance. While the benefits are obvious, companies have struggled with how to achieve this vision. But now there is a practical solution. To read more, click here. » read more

Finding And Fixing ML’s Flaws

By Ed Sperling - 02 May, 2018 - Comments: 0

OneSpin CEO Raik Brinkmann sat down with Semiconductor Engineering to discuss how to make machine learning more robust, predictable and consistent, and new ways to identify and fix problems that may crop up as these systems are deployed. What follows are excerpts of that conversation. SE: How do we make sure devices developed with machine learning behave as they're supposed to, and how do we... » read more

EDA In The Cloud (Part 2)

By Brian Bailey - 02 May, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

Inside UVM, Take Three

By Vatsal Choksi - 26 Apr, 2018 - Comments: 0

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Tech Talk: Improving Verification

By Ann Mutschler - 26 Apr, 2018 - Comments: 0

Frank Schirrmeister, senior group director for product management and marketing at Cadence, discusses how to verify different use cases, focusing on software, low-power designs, connectivity, and a variety of end markets. https://youtu.be/gK-0vmIWxJs » read more

Tail End Latency And Server Debug

By UltraSoC - 11 Apr, 2018 - Comments: 0

The rise of the heterogeneous multicore processor has enabled a massive increase in the ability of data centers to deliver advanced services to billions of users worldwide. But the complexity that is now possible has made the optimization of these services difficult to achieve. Providers of heterogeneous multicore SoCs have an opportunity to deliver the tools to make optimization of highly dist... » read more

When AI Goes Awry

By Ed Sperling - 26 Mar, 2018 - Comments: 0

The race is on to develop intelligent systems that can drive cars, diagnose and treat complex medical conditions, and even train other machines. The problem is that no one is quite sure how to diagnose latent or less-obvious flaws in these systems—or better yet, to prevent them from occurring in the first place. While machines can do some things very well, it's still up to humans to devise... » read more

Debugging Debug

By Brian Bailey - 22 Feb, 2018 - Comments: 2

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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