tag: debug

Formal Abstraction And Coverage
By Brian Bailey - 28 Jun, 2018 - Comments: 0

For the past three years, Oski Technology has facilitated a gathering of formal verification experts over dinner to discuss the problems and issues that they face. They discuss techniques they have been attempting with formal verification technologies, along with the results they have been achieving. Semiconductor Engineering was there to record that conversation and to condense it into the ... » read more

Verdi Transaction Debug Platform
By Synopsys - 27 Jun, 2018 - Comments: 0

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

Generating And Debugging Constraints For High-Speed Serial Instruments
By NI - 11 Jun, 2018 - Comments: 0

This white paper addresses the specific need for designing constraints into your NI PXIe-6591R or PXIe-6592R High Speed Serial project. Constraints are an often overlooked requirement of the project and can take several weeks to analyze timing requirements on a design, implement constraints, and achieving successful compilations that pass timing. This guide will help reduce the amount of time s... » read more

Machine Learning’s Limits (Part 1)
By Ed Sperling - 07 Jun, 2018 - Comments: 0

Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation. SE: Where are we with machine learning? What problems still have to be resolved? Aitken: We're in a state where thi... » read more

FPGAs Becoming More SoC-Like
By Ann Mutschler - 04 Jun, 2018 - Comments: 1

FPGAs are blinged-out rockstars compared to their former selves. No longer just a collection of look-up tables (LUTs) and registers, FPGAs have moved well beyond into now being architectures for system exploration and vehicles for proving a design architecture for future ASICs. This family of devices now includes everything from basic programmable logic all the way up to complex SoC devices.... » read more

Measuring And Analyzing SoC Performance With Verdi Performance Analyzer
By Synopsys - 23 May, 2018 - Comments: 0

SoC performance is a key competitive advantage in the marketplace. The choice and configuration of SoC components—protocol IP and interconnects, is geared towards maximizing overall SoC performance. A case in point is the use of HBM (High Bandwidth Memory) technology and controllers. Currently in its third generation, HBM boasts high-performance while using less power in a substantially small... » read more

Optimizing Your DRC Debug Can Reap Big Productivity Gains
By Srinivas Velivala - 10 May, 2018 - Comments: 0

Debugging design violations found by design rule checking (DRC) has always taken a significant share of the time needed to get a design to tapeout. And debug time only increases as the number and complexity of DRC expands with each new process node. Any steps you can take to make your DRC debug process more efficient directly improves your productivity. One technique for minimizing debug tim... » read more

Digital Twins: Making The Vision Achievable
By Ansys - 09 May, 2018 - Comments: 0

Few business concepts are generating the buzz of digital twins — product replicas that can help target performance issues and allow for true predictive maintenance. While the benefits are obvious, companies have struggled with how to achieve this vision. But now there is a practical solution. To read more, click here. » read more

Finding And Fixing ML’s Flaws
By Ed Sperling - 02 May, 2018 - Comments: 0

OneSpin CEO Raik Brinkmann sat down with Semiconductor Engineering to discuss how to make machine learning more robust, predictable and consistent, and new ways to identify and fix problems that may crop up as these systems are deployed. What follows are excerpts of that conversation. SE: How do we make sure devices developed with machine learning behave as they're supposed to, and how do we... » read more

EDA In The Cloud (Part 2)
By Brian Bailey - 02 May, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

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