tag: debug

Post-Silicon Validation Using Formal Analysis
By Various Writers - 09 Apr, 2014 - Comments: 0

Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employ... » read more

The Week In Review: Design
By Ed Sperling - 27 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a major new release of its place and route tool, the centerpiece of its physical design platform, offering up to 10X improvement in speed—a combination of 5X faster implementation and 2X larger capacity. Co-CEO Aart de Geus called it the most significant product in the company’s history. Synopsys also rolled out an AMS verification platform to accelerate regres... » read more

Big Shift In SoC Verification
By Ed Sperling - 17 Mar, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

When I Grow Up, I Want To Be A Software Programmer
By Tom De Schutter - 19 Dec, 2013 - Comments: 0

To keep up with the continuous introduction of new gadgets and capabilities in our smartphones, cars, houses and stores, it is clear that we need more software programmers. That is why multiple companies are coming up with new and innovative ways to introduce people — especially children — to programming. To lure them, the makers of these programming products try to mask the programming asp... » read more

The Race For Better Verification
By Graham Bell - 21 Nov, 2013 - Comments: 0

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis us... » read more

Experts At The Table: Debug
By Ed Sperling - 31 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: There are separate areas being created in devices, s... » read more

Experts At The Table: Debug
By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

Experts At The Table: Debug
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: What are the big issues with debug? ... » read more

How Much Verification Can One Engineer Handle?
By Frank Schirrmeister - 25 Sep, 2013 - Comments: 0

By Frank Schirrmeister When reviewing the agenda of our upcoming Verification Summit here in San Jose this Thursday, the question came to mind of who can actually execute the required complex verification tasks. Can they understand enough detail in hardware, software, and the system aspects to efficiently rid the design of bugs? The reality is that the task requires not one engineer who can do... » read more

Power-Up Low-Power Verification
By Adam Sherer - 09 May, 2013 - Comments: 0

By Adam Sherer When facing low-power verification in the SoC world, everyone could use a few power-ups just like Nintendo’s little plumber, Mario. Sure, Mario could run and jump through a lot of terrain, but when he hit some new challenges he could rely on some new tools and techniques to get him through. Completing your first SoC with a single power control module (PCM) and domain is lik... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy