tag: defects

What Machine Learning Can Do In Fabs
By Mark LaPedus - 25 Mar, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. L-R:... » read more

Defect Evolution In Next Generation, Extreme Ultraviolet Lithography
By Coventor - 18 Mar, 2020 - Comments: 1

Extreme ultraviolet (EUV) lithography is a promising next generation lithography technology that may succeed optical lithography at future technology nodes. EUV mask infrastructure and manufacturing of defect-free EUV mask blanks is a key near term challenge in the use of EUV lithography. Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of sem... » read more

Making Light More Reliable
By Ed Sperling - 11 Feb, 2020 - Comments: 0

The buzz around photonics in packages and between packages is growing. Now the question is whether it will work as expected, and where it will be useful. Replacing electrical with optical signals has been on the technology horizon for some time. Light moves faster through fiber than electrons through copper. How much faster depends upon the diameter of the wires, the substrate and interconne... » read more

Things That Go Bump In The Daytime
By Ed Sperling - 14 Jan, 2020 - Comments: 0

There is no argument that autonomous technology is better at certain things than systems controlled by people. A computer-guided system has only one mission — to stay on the road, avoid object, and reach the end destination. It doesn't get tired, text, or look out the window. And it can park within a millimeter of a wall or another vehicle without hitting it, and do that every time — as lon... » read more

Making 3D Structures And Packages More Reliable
By Ed Sperling - 14 Jan, 2020 - Comments: 0

The move to smaller vertical structures and complex packaging schemes is straining existing testing approaches, particularly in heterogeneous combinations on a single chip and in multi-die packages. The complexity of these devices has exploded with the slowdown in scaling, as chipmakers turn to architectural solutions and new transistor structures rather than just relying on shrinking featur... » read more

Extreme Quality Semiconductor Manufacturing, Part 1: Automotive
By Ben Tsai - 14 Jan, 2020 - Comments: 0

By Ben Tsai and Cathy Perry Sullivan Across the full range of semiconductor device types and design nodes, there is a drive to produce chips with significantly higher quality. Automotive, IoT and other industrial applications require chips that achieve very high reliability over a long period of time, and some of these chips must maintain reliable performance while operating in an environmen... » read more

Scan Diagnosis
By Ed Sperling - 20 Dec, 2019 - Comments: 1

Jayant D’Souza, product manager at Mentor, a Siemens Business, explains the difference between scan test and scan diagnosis, what causes values in a scan test to change, how this can be used to hone in on the actual cause of a failure in a design, and how to utilize test hardware more efficiently. » read more

Finding Defects In IC Packages
By Mark LaPedus - 17 Dec, 2019 - Comments: 0

Several equipment makers are ramping up new inspection equipment to address the growing defect challenges in IC packaging. At one time, finding defects in packaging was relatively straightforward. But as packaging becomes more complex, and as it is used in markets where reliability is critical, finding defects is both more difficult and more important. This has prompted the development of a ... » read more

Reliability At 5nm And Below
By Ed Sperling - 10 Dec, 2019 - Comments: 2

The best way to figure out how a chip or package will age is to bake it in an oven, heat it in a pressure cooker, and stick it in a freezer. Those are all standard methods to accelerate physical effects and the effects of aging, but it's not clear they will continue working as chips shrink to 5nm and 3nm, or as they are included in multi-die packages. Extending any of those kitchen-like appr... » read more

The 3 Main Obstacles To Zero DPPM And How To Overcome Them
By Optimal Plus - 11 Nov, 2019 - Comments: 1

As we all well know, there are multiple mission critical applications in today’s “Age of Smart,” that are calling for zero DPPM (defective parts per million) in semiconductors and electronic systems. In industries such as automotive, medical, aerospace, and more, where lives are at stake, defective parts are not an option. The quality imperative However, with the ever-growing complexity o... » read more

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