tag: design rules

Boosting Analog Reliability
By Ed Sperling - 17 Jan, 2019 - Comments: 0

Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

How To Improve Analog Design Reuse
By Ann Mutschler - 14 Nov, 2018 - Comments: 0

Digital circuit design is largely automated today, but most analog components still are designed manually. This may change soon. As analog design grows increasingly complex and error-prone, design teams and tool vendors are focusing on how to automate as much of the design of analog circuits as possible. Analog design is notoriously difficult and varied. It can include anything from power ma... » read more

Variation’s Long, Twisty Tail Worsens At 7/5nm
By Ed Sperling - 20 Sep, 2018 - Comments: 1

Variation is becoming a bigger challenge at each new node, but not just for obvious reasons and not always from the usual sources. Nevertheless, dealing with these issues takes additional time and resources, and it can affect the performance and reliability of those chips throughout their lifetimes. At a high level, variation historically was viewed as a mismatch between what design teams in... » read more

In-Design Power Rail Analysis
By Ed Sperling - 17 Jul, 2018 - Comments: 0

Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

Emulation-Driven Implementation
By Ed Sperling - 22 Jun, 2018 - Comments: 0

Tech Talk: Haroon Chaudhri, director of Prime Power at Synopsys, talks about how to shorten time to market and increase confidence in advanced-node designs, while also reducing the amount of guard-banding and improving design freedom. https://youtu.be/xT3CIqjnaBk » read more

Tech Talk: eFPGA Timing
By Ed Sperling - 03 May, 2018 - Comments: 0

Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

More Nodes, New Problems
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

Mashup At 7nm
By Ed Sperling - 19 Apr, 2018 - Comments: 0

The merger of two standards organizations typically falls well below the radar of most engineers, but folding the ESD Alliance (formerly known as the EDA Consortium) into SEMI is a different kind of deal. Ever since the introduction of finFETs and multiple patterning, EDA tools have become an integral part of the development of new manufacturing processes. Without those tools, there is no po... » read more

Design Rule Complexity Rising
By Ed Sperling - 19 Apr, 2018 - Comments: 0

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

The Next 5 Years Of Chip Technology
By Ed Sperling - 14 Mar, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay... » read more

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