tag: design

Virtuoso ADE Assembler
By Cadence - 26 May, 2021 - Comments: 0

Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

Using Cliosoft SOS Design Management Platform In The Cloud
By Cliosoft - 31 Mar, 2021 - Comments: 0

In this eBook, we will talk about the various scenarios for how designers can leverage Cliosoft’s SoC design management platform in the cloud (Amazon Web Services and Google Cloud Platform) to successfully tapeout their SoCs. Click here to access the eBook. » read more

When Is Verification Done?
By Ann Mutschler - 25 Feb, 2021 - Comments: 0

Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

5G NR Design For eMBB
By Cadence - 24 Feb, 2021 - Comments: 0

This white paper examines the design challenges for eMBB products and provides examples of how these challenges can be overcome using the co-design capabilities in Cadence AWR Design Environment software. Click here to download with registration. » read more

The Evolution Of Digital Twins
By Brian Bailey - 03 Aug, 2020 - Comments: 1

Digital twins are starting to make inroads earlier in the chip design flow, allowing design teams to develop more effective models. But they also are adding new challenges in maintaining those models throughout a chip's lifecycle. Until a couple of years ago, few people in the semiconductor industry had even heard the term "digital twin." Then, suddenly, it was everywhere, causing confusion ... » read more

Designer And IP Tracks Swell With Focus On ML, Security And Traditional EDA Methodologies
By Michelle Clancy - 13 Jul, 2020 - Comments: 0

What are designers keenly interested in as the 57th Design Automation Conference (DAC) approaches? If you said machine learning (ML), you’d be only partially right. Based on designer and IP tracks submissions to the 57th edition of the venerable electronics-industry event, ML – how to design with it and optimize EDA tools and flows using it – is a hot topic. But so too are more traditi... » read more

An Eye For An AI
By Ed Sperling - 01 Jun, 2020 - Comments: 0

AI comes in multiple forms and flavors. The challenge is choosing the right one for the right purpose, and recognizing that just because AI can be applied to a particular process or problem doesn't mean it should be. While AI has been billed as a ideal solution for just about every problem, there are three primary requirements for a successful application. First, there needs to be sufficient q... » read more

RTL Architect: Simply Better RTL
By Synopsys - 27 May, 2020 - Comments: 0

Electronic devices play a key role in society. They connect us to one another through voice, video and chat. They entertain, educate, protect and heal us in new and ever-expanding ways. They have changed the way we work, live and play. Silicon chips are the fast beating heart (2 to 3 billion beats per second) of these devices. For decades, the relentless advancements in semiconductor process te... » read more

Test Is Becoming A Horizontal Process
By Ed Sperling - 10 Mar, 2020 - Comments: 3

Semiconductor test, once a discrete part of a well-orchestrated series of manufacturing steps, is looking more like a process that extends from the early concept stage in design to the end of life of whatever system that chip ultimately is used for. This has important ramifications for safety-critical markets in general, and the semiconductor industry in particular. Both worlds have been inc... » read more

Better, Not Best
By Brian Bailey - 26 Nov, 2019 - Comments: 0

The semiconductor industry has been lulled into a particular way of thinking by Moore's Law. It is like the age-old joke — you don't have to outrun a bear, you only have to be faster than your companion. The same has held true for designs. There is little to no point being the best, you only have to be good enough to be better than the competition. That sets the bar. Best is also relative.... » read more

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