tag: die shift

3D Structures Challenge Wire Bond Inspection
By Karen Heyman - 09 May, 2023 - Comments: 1

Adding more layers in packages is making it difficult, and sometimes impossible, to inspect wire bonds that are deep within the different layers. Wire bonds may seem like old technology, but it remains the bonding approach of choice for a broad swath of applications. This is particularly evident in automotive, industrial, and many consumer applications, where the majority of chips are not de... » read more

Managing Thermal-Induced Stress In Chips
By Karen Heyman - 16 Feb, 2023 - Comments: 0

At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

Big Changes In Materials And Processes For IC Manufacturing
By Ed Sperling And Laura Peters - 21 Apr, 2022 - Comments: 3

Rama Puligadda, CTO at Brewer Science, sat down with Semiconductor Engineering to talk about a broad set of changes in semiconductor manufacturing, packaging, and materials, and how that will affect reliability, processes, and equipment across the supply chain. SE: What role do sacrificial materials play in semiconductor manufacturing, and how is that changing at new process nodes? Puliga... » read more

Future Challenges For Advanced Packaging
By Mark LaPedus - 20 Jan, 2022 - Comments: 1

Michael Kelly, vice president of advanced packaging development and integration at Amkor, sat down with Semiconductor Engineering to talk about advanced packaging and the challenges with the technology. What follows are excerpts of that discussion. SE: We’re in the midst of a huge semiconductor demand cycle. What’s driving that? Kelly: If you take a step back, our industry has always ... » read more

Next Steps For Panel-Level Packaging
By Mark LaPedus - 20 Dec, 2021 - Comments: 1

Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

MEMS: New Materials, Markets And Packaging
By Ed Sperling - 28 Jul, 2021 - Comments: 1

Semiconductor Engineering sat down to talk about future developments and challenges for microelectromechanical systems (MEMS) with Gerold Schropfer, director of MEMS products and European operations in Lam Research's Computational Products group, and Michelle Bourke, senior director of strategic marketing for Lam's Customer Support Business Group. What follows are excerpts of that conversation.... » read more

Investigation and Methods Using Various Release and Thermoplastic Bonding Materials to Reduce Die Shift and Wafer Warpage for eWLB Chip-First Processes
By Brewer Science - 14 Aug, 2019 - Comments: 0

Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-vias (TSVs). One approa... » read more

Material Solutions For FOWLP Die Shift And Wafer Warpage
By Shelly Fowler - 20 Jun, 2019 - Comments: 0

By Shelly Fowler Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower-profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-via... » read more

Lithography Challenges For Fan-out
By Mark LaPedus - 12 Feb, 2019 - Comments: 3

Higher density fan-out packages are moving toward more complex structures with finer routing layers, all of which requires more capable lithography equipment and other tools. The latest high-density fan-out packages are migrating toward the 1µm line/space barrier and beyond, which is considered a milestone in the industry. At these critical dimensions (CDs), fan-outs will provide better per... » read more

Litho Options For Panel Fan-out
By Mark LaPedus - 06 Nov, 2017 - Comments: 2

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today’s fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

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