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Big Changes In Materials And Processes For IC Manufacturing

Brewer Science’s CTO drills down into everything from purity and bonding to scaling and variation.

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Rama Puligadda, CTO at Brewer Science, sat down with Semiconductor Engineering to talk about a broad set of changes in semiconductor manufacturing, packaging, and materials, and how that will affect reliability, processes, and equipment across the supply chain.

SE: What role do sacrificial materials play in semiconductor manufacturing, and how is that changing at new process nodes?

Puligadda: We are talking about materials that perform certain functions that enable fabrication processes and are removed subsequently. One of the challenges in the new nodes is that these films are getting thinner and thinner. We’re in the single-nanometer range for these thin films, where they are expected to continue to be uniform and defect-free. Another important challenge is planarization of a wide range of features without bias, and also filling large or high-aspect ratio gaps. For most of the future nodes, the structures will continue to get taller. Additionally, there is a need to withstand very high processing temperatures.

SE: And quality now is being measured in parts per quadrillion, right?

Puligadda: Exactly. Our materials are expected to not have any defects on the wafer when coated and after they are removed.

SE: Related to that, Brewer Science pointed out several years ago that not everyone in the supply chain is focused on semiconductors, so their goals for purity were not stringent enough. Has that improved?

Puligadda: Yes, but we still have to push our suppliers to meet standards they didn’t even know about before — especially those that predominantly make materials for different industries. They never had to worry about parts per quadrillion. That’s a relatively small number of our suppliers, though. Most are delivering quite well now, and where it’s not possible to find that level of purity, we’re working toward vertical integration so we can make those high-quality monomers and raw materials ourselves.

SE: With regard to planarization materials, what steps are those being used for? Are there sacrificial materials in vias and interconnects?

Puligadda: Not always. But in a lot of cases, they have to do additional processing so they can fabricate structures in other areas of the wafer, or on top of the structure that they’ve already built. This is when they want a material that temporarily fills the gaps or planarizes the structures underneath. That material has to be removed without residue, and as we move to smaller nodes, that is one of the biggest challenges.

SE: How is that done?

Puligadda: It can be wet or dry, depending on the structure. The high-aspect structures can be very delicate and must be protected through the cleaning process, as well, so they can’t use agitation or anything harsh. Any combination of wet or dry is possible.

SE: Are you seeing new issues stemming from advanced packaging?

Puligadda: The newest trend we’re seeing is hybrid bonding. That requires extremely flat, defect-free surfaces in order to bring them together reliably.

SE: Basically, you’re trying to melt the copper evenly, but in the past you could probably perfect this process across a billion-chip run. Now, we’re seeing smaller batches of more customized designs, with the potential for die shifting. Is that as a big a problem as everyone originally thought?

Puligadda: Die shift is a major challenge. It used to be that the whole system was on a chip. Now they’ve broken it down or disaggregated into chiplets. We can put them on top of each other, or side by side, or wherever we need to integrate various functionalities in a package. It’s basically heterogeneous integration. We’re joining one chip on top of the other, or on top of a wafer, and you can’t have any die-shifting at these very small dimensions. We are working in that area, and have a few technologies that make it possible.

SE: Can you give an example?

Puligadda: One approach is to apply an adhesive material on a temporary carrier and populate that carrier with dies. You can either do over-molding or attach other die to it, or attach it to the wafer, and you can do that without having any shift in the dies. We’re able to do whatever that process requires with very minimal shift in the die. But as the die sizes go down, and in certain applications these can be pretty small, then this isn’t the best solution. It works, but it’s not very elegant. So we’re working on more elegant solutions where you could attach the die directly to the wafer, and over time that will reduce the cost for customers.

SE: Does it get harder as more circuitry is added into RDL? Basically, you’re building that on both sides of the wafer.

Puligadda: It depends on the broad packaging scheme. If you’re building RDL first, we have materials that allow that. You can build the RDL on a carrier or on a substrate before you put down your chip. We definitely are enabling that with some of our materials, and those materials can be removed without residue.

SE: Will adding pads on the back side of the wafer be a problem?

Puligadda: I can understand why that is needed, because they have to deliver power to the device, which is much smaller now. If you make the lines too small, you need to put the power delivery network somewhere. They’re also using the backside of the wafer to do that. There are other challenges, too. Because you’ve already built your devices on the front end, you need to do this on the back without damaging anything on the front.

SE: There are a lot of moving parts here between bonding/debonding, sacrificial vs. permanent materials, chiplets, mechanical stress from heterogeneous integration. What’s the outlook?

Puligadda: It is getting complicated, especially because we are dealing with integration in multiple dimensions with wafers and substrates and panels.


Fig. 1: Temporary wafer bonding is critical for ultrathin wafer handling. Source: Brewer Science

SE: You almost need a blueprint for all of these different pieces, right?

Puligadda: Yes, and the bonding process cannot be decoupled from the debonding process or the process in between. Once you bond the wafers, you may have a material that has to withstand very high temperatures, or it needs to be resistant to chemicals because there are some really harsh chemicals that are used. And then you may have something that needs to bond at room temperature, but which also can withstand high temperatures and then be debonded at room temperature. You can achieve all of that — very low stress bonding with all of these middle processes that are very high stress and harsh — but it takes really clever design of materials to be able to do that.

SE: How much is Brewer Science getting pulled into the automotive world, where bonds also have to withstand intense vibration and other mechanical stresses?

Puligadda: We have a few products on the permanent bonding side. They stay on the device, and they have to prove reliable throughout the lifetime of the device and the use case for that device. The automotive area is extremely stringent, and materials have to go through a very extensive qualification process.

SE: One of the new technologies is photonic debonding. What is that and why is it becoming important now?

Puligadda: We’ve been doing temporary bonding for about 15 years, and we started out with chemical removal using perforated wafers. Then we came up with slide debonding, where you melt the adhesive and slide the carrier against the wafer to separate them. Then we went on to mechanical debonding, where you introduce some release layers on the carrier side, which allows you to mechanically separate them after all the processing is done. Then came laser debonding, where we put in release layers, which are responsive to laser. And now we’re looking at what we call photonic debonding, which uses UV instead of lasers. The goal is to be able to do just one exposure and not have to raster, as in the case of laser. So it’s going to be better for cost of ownership.

SE: What impact will chiplets have on your strategy?

Puligadda: When we first started, it was mostly wafer-level processing, so we developed temporary wafer-to-wafer bonding and debonding. Because of the advent of chiplets, it has morphed into more die-to-wafer or die-to-die. We are still doing temporary bonding, but of chiplets, or small chips, until they get bonded to another wafer or another chip, which is what it has evolved into. But that needed a lot of change in the design of that material, as well, because we are dealing with smaller pieces now.

SE: So the impact is due to smaller dimensions, right?

Puligadda: Yes, and that’s why we have new considerations. In the past, we were more worried about grinding and chipping and alignment. Now, in addition to alignment, we also have to deal with die shift and cleaning.

SE: How does variation affect all of this, particularly materials?

Puligadda: Variation shows up in many different ways. Everybody has a different scheme, and there are multiple ways of achieving what you’re looking for in a package. The goal is always performance, power, area, and cost, so what is the best possible combination to achieve that. We’re seeing reconfigured wafers in different mold compounds, and those mold compounds are not the same everywhere. They’re very flexible, in some cases, and very rigid in other cases, highly stressed in one case and not in the other. We have to deal with all of that, in addition to different variability in the process schemes, and in our materials and process technology.

SE: And it’s additive, too, right? Individually these might cause an issue, but multiple sources of variation might.

Puligadda: Yes, that is correct.

SE: Does this require new equipment?

Puligadda: Yes. New equipment will be needed for really thin wafers or reconfigured wafers. It’s not just about handling the extremely thin substrates, though. You want them to be ultra clean, but how do you clean something that’s so thin and delicate or highly stressed? We’re already seeing a big need when it comes to hybrid bonding.

SE: You mentioned reconfigured wafers. What are those?

Puligadda: eWLB was the original form of it, where chips are embedded in a polymeric mold compound to be able to use the area around it for RDL.

SE: Most of what has happened in semiconductor manufacturing has been heavily weighted toward subtraction rather than growing structures on a wafer or die. Do you expect more additive approaches will ever become commercially viable?

Puligadda: We have started to see that people are getting serious about additive or selective deposition of materials, instead of putting down a blanket layer, patterning it, and removing areas they don’t want. When it comes to etching on these very thin layers, you’re landing on a very thin etch stop, or on a different layer that’s very, very thin. This leaves very little margin for errors or overshoot. We’ve had conversations about selectively depositing in one area or another, and we are getting closer to additive manufacturing or additive processing. We’re still not quite there. At the same time, I don’t think patterning and etch are going away anytime soon.

SE: What changes on the materials side when we start using high-NA EUV?

Puligadda: We’ve done a mock-up for high-NA EUV and what challenges that will bring. There are tools to simulate that, and we’ve been working to identify challenges. But it’s still a little early for launching products for this technology.

SE: Is it mostly the under-layers that you’re working on for high-NA EUV?

Puligadda: Yes, mostly. We want to enable our customers’ roadmaps. Most have expressed very clearly that they are going for high-NA, maybe even before multiple patterning. So, we’re working closely with our customers and with Imec to stay on that roadmap.

SE: Where do you see panel-level fan-out going? Is it real?

Puligadda: There is not much volume, but there are people doing it for some specific types of devices. Our temporary and permanent bonding materials work regardless of whether it’s for a panel or a wafer. We just had to find different ways of depositing them onto larger structures.

SE: Any new issues as scaling continues down to 3/2/1nm?

Puligadda: With materials, it’s learning how to deposit these films with precision, and remove them with precision, like deposition and etch. That’s the biggest challenge for the industry, in general. The precision that’s needed will probably require new equipment. These new nodes will require all kinds of new materials and processes that we’ll have to learn to work with, from different chemistries to different temperature conditions. And when we actually get down to 2D materials, which will happen at some point in time, we are only going to have one or two atomic layers. There will be new interfaces to deal with more delicate structures.

SE: Tolerances are extremely tight at the most advanced nodes, and materials need to be extremely pure. What impact will continued scaling have on the supply chain?

Puligadda: There will be some changes in the device structures themselves, which will create some new patterning needs that we have to address. You need very smart designs for the materials, because you have to be able to put it down, withstand all the processes it’s going to go through, and then come out with no added signature anywhere. That requires clever design, and it requires very high quality in manufacturing.

SE: Looking at this from a higher level of abstraction, design is going in two directions. One is more granular, the other more holistic. How good is the material? How well was it put down, from a whole chip to a whole wafer? But then, you also have to worry about whether a chiplet is properly seated on a pad and were all the connections done correctly? There are a lot of pieces that all need to work together, right?

Puligadda: Yes, and we cannot just worry about our piece. We have to worry about the whole system, the whole process, because what is used as a bonding material or sacrificial material has implications throughout the process, and then even for the device itself if something isn’t properly removed.

SE: What’s the impact of this on different processes?

Puligadda: In the past, the packaging side never used to talk to the front of the line. They were completely disconnected. But now they are recognizing that what happens at the front end affects the back end, so now they have to work more closely together. So the fabs are setting the requirements, and they’re also providing more feedback.

SE: What’s the most interesting change from Brewer Science’s perspective?

Puligadda: It’s the new kinds of materials. Without new materials, and innovations in materials, we’re not going to realize the new roadmaps. We are working on enabling all of those roadmaps with new materials, whether it’s for enabling fabrication or with materials that stay on the device.

SE: Is cost a big concern, particularly with new materials like molybdenum?

Puligadda: Yes, but for ruthenium, there are certain advantages, and for molybdenum, another set. So it’s hard to decide which of these advantages to go with.

SE: There’s still a lot of concern about things like line-edge roughness with EUV and high-NA EUV. What’s happening on the materials side to address that?

Puligadda: There’s a lot of work going on in the EUV resists area. It started off with CARs (chemically amplified resists) and moved onto metal oxide resists and other chemistries that don’t use CARs. There are also some CVD based resists that claim better roughness and overcome other challenges that CAR resists have. There are many possibilities in EUV, and there are tradeoffs everywhere. EUV is one place where there is no universal solution. You need specific patterning layers for contacts holes or for the line and space patterns. You can’t just fit one or the other. There are all kinds of possibilities at this point.



3 comments

Chris Ethen says:

I would like to know about the QA tools used for these processes. Will darkfield systems be in play or another technology?

Laura Peters says:

For new materials, darkfield could be used but likely a combination of brightfield (light) and darkfield (laser) using algorithms to identify critical defects as discussed here: https://semiengineering.com/auto-chipmakers-dig-down-to-10ppb/ and here: https://semiengineering.com/challenges-grow-for-finding-chip-defects/. Multibeam e-beam tools are available for yield ramp and debug but haven’t made it into the fab yet for defect detection.

Florian says:

“for ruthenium, there are certain advantages, and for molybdenum, another set. So it’s hard to decide which of these advantages to go with”…

I am wondering: Shouldn’t this be already decided, as it is relevant for the 2 nm node which will already be produced in 2024. Not much time to integrate a chosen precursor into the CVD process, am I right?

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