Single Vs. Multi-Patterning Advancements For EUV

By Gregory Haley - 20 Jun, 2024 - Comments: 0

As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication

By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

International Roadmap for Devices and Systems lithography roadmap

By Technical Paper Link - 19 Nov, 2021 - Comments: 0

Abstract: "Background: Planned improvements in semiconductor chip performance have historically driven improvements in lithography and this is expected to continue in the future. The International Roadmap for Devices and Systems roadmap helps the industry plan for the future. Aim: The 2021 lithography roadmap shows requirements, possible options, and challenges for the next 15 years. Resul... » read more

Gearing Up For High-NA EUV

By Mark LaPedus - 21 Oct, 2021 - Comments: 2

The semiconductor industry is moving full speed ahead to develop high-NA EUV, but bringing up this next generation lithography system and the associated infrastructure remains a monumental and expensive task. ASML has been developing its high-numerical aperture (high-NA) EUV lithography line for some time. Basically, high-NA EUV scanners are the follow-on to today’s EUV lithography systems... » read more

EDA In The Cloud

By Ed Sperling - 18 Feb, 2020 - Comments: 0

Michael White, director of product marketing for Calibre physical verification at Mentor, a Siemens Business, looks at the growing compute requirements at 7, 5 and 3nm, why the cloud looks increasingly attractive from a security and capacity standpoint, and how the cloud as well as new lithography will affect the cost and complexity of developing new chips. » read more

Single Vs. Multi-Patterning EUV

By Mark LaPedus - 25 Mar, 2019 - Comments: 5

Extreme ultraviolet (EUV) lithography finally is moving into production, but foundry customers now must decide whether to implement their designs using EUV-based single patterning at 7nm, or whether to wait and instead deploy EUV multiple patterning at 5nm. Each patterning scheme has unique challenges, making that decision more difficult than it might appear. Targeted for 7nm, single pattern... » read more

Inside FD-SOI And Scaling

By Mark LaPedus - 15 Jun, 2017 - Comments: 5

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

Will EUV Kill Multi-Patterning?

By David Abercrombie - 19 Jan, 2017 - Comments: 0

When I first began working on double-patterning (DP) tools back in late 2010, there was already talk that it might be a fruitless, or at a minimum, very short-lived project, as extreme ultraviolet (EUV) lithography was just around the corner and would make all multi-patterning (MP) obsolete. Well, as I begin my seventh year on this project, I can hear echoes of Mark Twain as clearly, the report... » read more

Fill/Cut Self-Aligned Double-Patterning

By David Abercrombie - 17 Nov, 2016 - Comments: 0

By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke Self-aligned double patterning (SADP) is an alternative double-patterning process to the traditional litho-etch-litho-etch (LELE) approach used in most advanced production nodes. The main difference between the two approaches is that in LELE, the layout is divided between two masks, and the second mask is aligned with resp... » read more

450mm And Other Emergency Measures

By Ed Sperling - 22 Sep, 2016 - Comments: 0

Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months. Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?