tag: DRAM

Memory-Computation Decoupling Execution To Achieve Ideal All-Bank PIM Performance
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling" was published by researchers at Korea University. "This paper proposed the memory-computation decoupled PIM architecture to provide the performance comparable to the all-bank PIM while preserving the standard DRAM interface, i.e., DRAM commands, powe... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

How Memory Design Optimizes System Performance
By John Koon - 21 Sep, 2022 - Comments: 0

Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 16 Sep, 2022 - Comments: 0

President Biden signed an executive order on Sept. 15, limiting foreign investments in U.S. technology by "competitor or adversarial nations" that are deemed a threat to national security. In the past, the Committee on Foreign Investment in the United States (CFIUS) largely limited its actions to the sale of U.S. companies. The new directive expands that to include investments involving "U.S. s... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

Finding the Scope of CXL-Enabled Tiered Memory System in Production
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

This new technical paper titled "TPP: Transparent Page Placement for CXL-Enabled Tiered Memory" is presented by researchers at University of Michigan and Meta Inc. Abstract (partial) "We propose a novel OS-level application-transparent page placement mechanism (TPP) for efficient memory management. TPP employs a lightweight mechanism to identify and place hot and cold pages to appropriate... » read more

An Escalation of Rowhammer To Rows Beyond Immediate Neighbors
By Technical Paper Link - 15 Aug, 2022 - Comments: 0

Researchers at Graz University of Technology, Lamarr Security Research, Google, AWS, and Rivos presented this new technical paper titled "Half-Double: Hammering From the Next Row Over" at the USENIX Security Symposium in Boston in August 2022. Abstract: "Rowhammer is a vulnerability in modern DRAM where repeated accesses to one row (the aggressor) give off electrical disturbance whose cumu... » read more

Data Integrity For JEDEC DRAM Memories
By Shyam Sharma - 19 Jul, 2022 - Comments: 0

With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b, and 1c nodes along with the DRAM device speeds going up to 8533 for LPDDR5 and 8800 for DDR5, data integrity is becoming a really important issue that the OEMs and other users have to consider as part of the system that relies on the correctness of data being stored in the DRAMs for system to work as designed. I... » read more

Reduce RowHammer Vulnerability By Reducing Wordline Voltage
By Technical Paper Link - 18 Jul, 2022 - Comments: 0

Researchers from ETH Zurich present a new technical paper titled "Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices." Abstract (Partial) "This is the first work to experimentally demonstrate on 272 real DRAM chips that lowering VPP reduces a DRAM chip's RowHammer vulnerability. We show that lowering VPP 1) increases the number of activat... » read more

DRAM Chips That Employ On-Die Error Correction & Related Reliability Techniques
By Technical Paper Link - 16 Jul, 2022 - Comments: 0

This new PhD thesis paper titled "Enabling Effective Error Mitigation in Memory Chips That Use On-Die Error-Correcting Codes" from ETH Zurich researcher Minesh Patel won the IEEE  William C. Carter Award in June 2022. Abstract "Improvements in main memory storage density are primarily driven by process technology scaling, which negatively impacts reliability by exacerbating various circu... » read more

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