Options Widen For Optimizing IoT Designs

By John Koon - 29 Mar, 2023 - Comments: 0

Creating a successful IoT design requires a deep understanding of the use cases, and a long list of tradeoffs among various components and technologies to provide the best solution at the right price point. Maximizing features and functions while minimizing costs is an ongoing balancing act, and the number of choices can be overwhelming. The menu includes SoC selection, OS and software proto... » read more

Tensilica DSPs Support In Eigen Library

By Cadence - 04 Jan, 2023 - Comments: 0

Eigen is a high-level C++ library of template headers for linear algebra, matrix and vector operations, geometrical transformations, numerical solvers, and related algorithms. Eigen is open-source software licensed under the Mozilla Public License 2.0 (MPL2). Eigen is implemented using the expression templates metaprogramming technique, meaning it builds expression trees at compile time... » read more

Accelerate The Algorithm To Silicon Development With Stratus HLS

By Cadence - 21 Dec, 2022 - Comments: 0

Growth in demand for artificial intelligence (AI) and digital signal processing (DSP) applications, coupled with advances in semiconductor process technology, drives increasingly denser SoCs. These complex SoCs further challenge the design team’s ability to meet performance, power, and area (PPA) goals within tight time-to-market windows. We need automated and targeted solutions that efficien... » read more

Tensilica DSP Code Generation Toolbox With MATLAB/Simulink

By Cadence - 07 Dec, 2022 - Comments: 0

MATLAB and Simulink are widely used for modeling and simulating real-time dynamical systems. To verify the performance of MATLAB/Simulink models of these systems in a real-time application, MATLAB/Simulink models are converted to embedded C code and executed on a target processor or its equivalent Instruction Set Simulator (ISS). To deploy the generated C code in a processor, the genera... » read more

Heterogeneous Redundant Circuit Design Approaches for FPGAs

By Technical Paper Link - 12 Jul, 2022 - Comments: 0

New research paper titled "Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs" from researchers at Nagasaki University. Abstract (Partial) "In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach foc... » read more

Designing Application-Specific Processors for Wireless 5G SoCs

By Synopsys - 25 May, 2022 - Comments: 0

Traditional architectures for wireless baseband applications are no longer adequate for recent and next-generation modem standards. Supporting complex and still evolving standards like 5G in a single modem is only possible by using SDR techniques, which place increasing demands on performance and power consumption on the SoC. ASIP architectures enable full customization of a processor, which... » read more

Meeting Processor Performance And Safety Requirements For New ADAS & Autonomous Vehicle Systems

By Fergus Casey - 02 Dec, 2021 - Comments: 1

By Fergus Casey and Srini Krishnaswami Innovation in today’s automotive industry is accelerating as companies race to be the market leader in safety and autonomous vehicles. With vehicle control moving from humans to the vehicles’ active safety systems, more sensors – cameras, radar, lidar, etc. – are being added to automotive systems. More sensors require more computational performa... » read more

A DSP For Implementing High-Performance Sensor Fusion On An Embedded Budget

By Markus Willems - 11 Nov, 2021 - Comments: 0

By Markus Willems and Pieter van der Wolf Sensor fusion refers to the combining of data from multiple sensors to obtain more complete and accurate results. By using the information provided by multiple sensing devices, it is possible to achieve better context awareness. Smart mobile devices, autonomous driving, smart home appliances, industrial control, and robotics are just a few of the app... » read more

What Is An xPU?

By Brian Bailey - 11 Nov, 2021 - Comments: 0

Almost every day there is an announcement about a new processor architecture, and it is given a three-letter acronym — TPU, IPU, NPU. But what really distinguishes them? Are there really that many unique processor architectures, or is something else happening? In 2018, John L. Hennessy and David A. Patterson delivered the Turing lecture entitled, "A New Golden Age for Computer Architecture... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 03 Sep, 2021 - Comments: 1

OEMs For some time, the automotive industry has suffered due to chip shortages in the market. And the chip shortages are spreading into other markets. In the latest news, GM plans to idle key truck plants amid chip shortages, according to a report from Bloomberg. “GM said eight of its 14 North American assembly plants will experience shutdowns this month because of chip shortages, includi... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?