Manufacturing Bits: April 29

By Mark LaPedus - 29 Apr, 2014 - Comments: 0

Silky e-beam lithography Tufts University has put a soft and silky spin on direct-write electron-beam lithography. Researchers used common silk as the resist material, enabling the production of photonic lattices, quantum dots and other structures. This approach is a green alternative to traditional and toxic resists. The silk-based resist is developed using a water-based process. It starts... » read more

One-on-One: Naoya Hayashi

By Mark LaPedus - 20 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the current and future challenges in the photomask industry with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP). SE: What are the big challenges for the photomask industry today? Hayashi: There are several challenges. Most of the challenges involve mask complexity. It is also quite difficult to handle the mask data, because it is ... » read more

Multi-Beam Begins To Shine

By Mark LaPedus - 17 Oct, 2013 - Comments: 0

After years of R&D and promises, multi-beam electron-beam technology is delayed and late to the market. The technology requires more funding and work than previously thought. And generally, the skepticism is running high for the technology. Finally, however, there is a ray of hope, and some momentum, in multi-beam—at least on the photomask front. Seeking to accelerate its multi-beam te... » read more

Executive Briefing: Getting Direct On Litho

By Mark LaPedus - 17 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down and talked with David Lam, principal of the David Lam Group, an investment and advisory firm. Lam is also the chairman of Multibeam, a multi-beam equipment startup for direct-write lithography and other applications. He founded Lam Research in 1980 and left as an employee in 1985. He served on Lam Research’s board for five years after that. SE: Multibeam ... » read more

Wanted: New Metrology Funding Models

By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing. Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology. ... » read more

Optical Lithography, Take Two

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes. Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC ... » read more

More Design Rules Ahead

By Ed Sperling - 25 Jul, 2012 - Comments: 0

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two converging factors will force these changes. First, the limits of current 193nm immersion lithography mean companies now must double pattern at 20nm, and potentially quadruple pattern at 14n... » read more

Fallback Plans

By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler With EUV lithography missing a few deadlines already, the semiconductor industry has begun to search for alternatives. None of these solutions is simple, of course, and it’s questionable whether they’re even economically viable. And even if EUV is ready for mass production by 14nm, there are new challenges that have to be dealt with—particularly in the space... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: e-beam