tag: ECTC

Week In Review: Manufacturing, Test
By Mark LaPedus - 11 Jun, 2021 - Comments: 0

Chipmakers SiFive has received a takeover offer from Intel, according to a report from Bloomberg. The asking price is more than $2 billion. ------------------------------------------------------------------ IBM has filed suit against GlobalFoundries (GF), alleging fraud and breach of contract committed by GF. IBM’s suit, filed in the Supreme Court of the state of New York, seeks relief... » read more

Manufacturing Bits: June 7
By Mark LaPedus - 07 Jun, 2021 - Comments: 0

High-voltage superjunction SiC devices The University of Warwick and Cambridge Microelectronics have presented a paper on the latest effort to develop of a new type silicon carbide (SiC) power device called a SiC superjunction Schottky diode. Researchers have simulated and optimized the development of 4H-SiC superjunction Schottky diodes at a voltage class of 1700 volts, aiming for breakdow... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 04 Jun, 2021 - Comments: 0

Government policy The Malaysian government has extended its lockdown due to the pandemic until June 14, a move that may impact the global electronics supply chain, according to TrendForce. Malaysia recently implemented MCO 3.0 (Movement Control Order), the nation’s pandemic control measure. Malaysia is home to many fab equipment, packaging and testing facilities, as well as passive compon... » read more

Making Chip Packaging More Reliable
By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

The Race To Much More Advanced Packaging
By Mark LaPedus - 23 Jul, 2020 - Comments: 2

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Manufacturing Bits: June 30
By Mark LaPedus - 30 Jun, 2020 - Comments: 0

1μm pitch wafer bonding At the recent IEEE Electronic Components and Technology Conference (ECTC), Imec presented a paper on a fine-pitch hybrid wafer-to-wafer bonding technology for heterogeneous integration. Imec described a way to enable hybrid bond pitches down to 1μm using a novel Cu/SiCN (copper/silicon-carbon-nitrogen) surface topography. Today, the industry is developing or shi... » read more

Manufacturing Bits: June 23
By Mark LaPedus - 23 Jun, 2020 - Comments: 0

Fan-out gas sensors At the recent IEEE Electronic Components and Technology Conference (ECTC), the University of California at Los Angeles (UCLA) and the Indian Institute of Science presented a paper on the development of a wearable MEMS gas sensor device based on a flexible wafer-level fan-out packaging technology. Researchers have demonstrated a gas sensor device or a personal environment... » read more

New Trends In Wafer Bonding
By Katherine Derbyshire - 21 Nov, 2019 - Comments: 0

Unable to scale horizontally, due to a combination of lithography delays and power constraints, manufacturers are stacking devices vertically. This has become essential as the proliferation of mobile devices drives demand for smaller circuit footprints, but the transition isn't always straightforward. Three-dimensional integration schemes take many forms, depending on the required interconne... » read more

Manufacturing Bits: June 25
By Mark LaPedus - 25 Jun, 2019 - Comments: 0

Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

What’s Next In Advanced Packaging
By Mark LaPedus - 20 Jun, 2019 - Comments: 3

Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

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