tag: EDA

Artificial Intelligence Wonderland
By Barry Pangrle - 30 Nov, 2023 - Comments: 0

Silicon Catalyst held its Sixth Annual Semiconductor Forum in Menlo Park on the SRI campus on November 9th. Richard Curtin, Managing Partner for Si Catalyst, opened the event with a reference to Arthur C. Clarke’s "2001: A Space Odyssey" and noted how remarkable it was that a novel written back in 1968 was able to foretell the direction of the computer industry over 50 years into the future. ... » read more

Improving AI Productivity With AI
By Ed Sperling - 28 Nov, 2023 - Comments: 0

AI is showing up or proposed for nearly all aspects of chip design, but it also can be used to improve the performance of AI chips and to make engineers more productive earlier in the design process. Matt Graham, product management group director at Cadence, talks with Semiconductor Engineering about the role of AI in identifying patterns that are too complex for the human brain to grasp, how t... » read more

What Can Go Wrong In Heterogeneous Integration
By Ed Sperling - 15 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom IC & PCB Group; and Tony Mastroia... » read more

Is Your Voltage Drop Flow Obsolete?
By Marc Swinnen - 13 Nov, 2023 - Comments: 0

Voltage drop at advanced nodes is a deadly serious problem that has become unmanageable with the methodologies used by most chip designers today. This article will cover the reasons why power integrity has risen to a top-of-mind concern and why it has become almost impossible for today’s EDA tools to measure and fix it. We will then look at some radical methodology rethinking that is needed t... » read more

Applications Of Large Language Models For Industrial Chip Design (NVIDIA)
By Technical Paper Link - 10 Nov, 2023 - Comments: 0

A technical paper titled “ChipNeMo: Domain-Adapted LLMs for Chip Design” was published by researchers at NVIDIA. Abstract: "ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: custom tokenizers, domain-ad... » read more

Rebalancing Test And Yield In IC Manufacturing
By Gregory Haley - 07 Nov, 2023 - Comments: 0

Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

Rethinking Design, Workflow For 3D
By Karen Heyman - 26 Oct, 2023 - Comments: 0

In the 3D world, where NAND has hundreds of layers and packages come in intricate stacks, fresh graduates and veteran engineers alike are being confronted with design challenges that require a rethinking of both classic designs and traditional workflows, but without breaking the laws of physics. “There are pockets of things that have been on 3D for quite some time,” said Kenneth Larson, ... » read more

Why Curvy Design Now? Less Change Than You Think And Manufacturable Today
By Jan Willis - 19 Oct, 2023 - Comments: 0

A curvilinear (curvy) chip, if magically made possible, would be smaller, faster, and use less power. Magic is no longer needed on the manufacturing side, as companies like Micron Technology are making photomasks with curvy shapes using state-of-the-art multi-beam mask writers today. Yet the entire chip-design infrastructure is based on the Manhattan assumption of 90-degree turns, even though i... » read more

Looking Forward To The New Chip Cycle
By Bob Smith - 19 Oct, 2023 - Comments: 0

Charles Shi, Principal and Senior Analyst at Needham & Company, LLC., remains upbeat about the EDA, IP and services business, or what SEMI refers to as the electronic system design (ESD) ecosystem. I recently spoke with Shi about his talk “Looking Forward to the New Chip Cycle” during the opening of the 2023 Design Automation Conference, collocated in July with SEMICON West in San Fra... » read more

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