ESD Alliance And SEMI Efforts To Combat Design Automation Software Piracy

By Bob Smith - 21 Mar, 2024 - Comments: 0

Piracy is a growing concern for all software providers, especially those of us with complex and specialized software, such as chip design automation software that is expensive to develop and maintain. That’s why the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, spearheaded an industry joint development effort to develop a server certification protocol that ... » read more

Blog Review: Mar. 13

By Jesse Allen - 13 Mar, 2024 - Comments: 0

Cadence's Geeta Arora explains the Address Translation Service in PCIe 6.0, which allows an I/O device to perform its own virtual to physical address translations without relying on the host's CPU to reduce latency and improve overall system performance. Synopsys' John Swanson, Jon Ames, Priyank Shukla, and Varun Agrawal highlight the upcoming 1.6T iteration of the Ethernet standard and the ... » read more

Blog Review: Mar. 6

By Jesse Allen - 06 Mar, 2024 - Comments: 0

Synopsys' Gandharv Bhatara notes that successfully deploying high-NA EUV will rely on computational lithography to provide accurate modeling of aberrations, compact 3D mask modeling, and expand inverse lithography to full-chip processing. Cadence's John Park argues for using a systematic and automated system for co-design and co-analysis of multi-die packages to reduce the margin for human e... » read more

Blog Review: Feb. 7

By Jesse Allen - 07 Feb, 2024 - Comments: 0

Synopsys' Ian Land, Kenneth Larsen, and Rob Aitken find that a new approach will be required to ensure that higher volume 3D heterogeneous integration (3DHI) designs can function reliably and successfully in aerospace, defense, and government systems. Siemens' John Golding provides a primer on the fundamental concepts related to signal integrity, including key topics such as transmission lin... » read more

EDA Back On Investors’ Radar

By Brian Bailey - 25 Jan, 2024 - Comments: 0

EDA is transforming from a staid but strategic sector into a hot investment market, fueled by strong earnings and growth, a clamoring for leading-edge and increasingly customized designs across new and existing markets, and the rollout of advanced technologies such as AI for a range of tools that will be needed to develop new architectures with much greater performance per watt. A confluence... » read more

Chip Industry Week In Review

By The SE Staff - 12 Jan, 2024 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan Renesas will acquire Transphorm, which designs and manufactures gallium nitride power devices, for about $339 million. GaN, which is a wide-bandgap technology, is used for high-voltage applications in a slew of markets, including EVs and EV fast chargers, as well as data centers and industrial applications. Cadence acquired Invecas, a provider o... » read more

Blog Review: Dec. 6

By Jesse Allen - 06 Dec, 2023 - Comments: 0

Cadence's Vinod Khera checks out potential implications of generative AI for EDA, including how it could increase the learning rate of students and reduce the rising verification cost. Synopsys' Kiran Vittal considers the driving factors behind RISC-V's growth and why it is becoming increasingly important for applications ranging from automotive to 5G mobile, AI, and data centers. Siemens... » read more

Looking Forward To The New Chip Cycle

By Bob Smith - 19 Oct, 2023 - Comments: 0

Charles Shi, Principal and Senior Analyst at Needham & Company, LLC., remains upbeat about the EDA, IP and services business, or what SEMI refers to as the electronic system design (ESD) ecosystem. I recently spoke with Shi about his talk “Looking Forward to the New Chip Cycle” during the opening of the 2023 Design Automation Conference, collocated in July with SEMICON West in San Fra... » read more

Blog Review: October 18

By Jesse Allen - 18 Oct, 2023 - Comments: 0

Siemens' Stephen Chavez suggests including analog mixed signal analysis and board level parasitics within the design process from the earliest electrical design stage and throughout final release of the PCB design. Synopsys’ Filip Thoen, Leonard Drucker, and Vivek Prasad highlight how the complexities and interdependencies of multi-die systems create new challenges for software bring-up, a... » read more

EDA Revenue Up Again

By Ed Sperling - 17 Oct, 2023 - Comments: 0

The EDA industry reached $3.963 billion in revenue in Q2, boosted by a 17.6% increase in computer-aided engineering and a 17.2% increase in IP physical design and verification, according to a just-released ESD Alliance Electronic Market Data report. The overall growth was offset by an accounting change in the IP business, which resulted in a 11.6% decline to $1.255 billion, as well as some w... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?