Speed Up P2P Resistance Debugging With Selective Highlighting


Point-to-point (P2P) resistance simulation calculates the effective parasitic resistance from one or more specified points (sources) to another set of points (sinks) on an integrated circuit (IC) layout. The results of these simulations are a key component in the verification of the robustness and reliability of IC layout interconnect—designers must have this information to accurately perform... » read more

Week In Review: Manufacturing, Test


Trade wars The trade war between the United States and China is escalating and it is here to stay. Victor Davis Hanson, a senior fellow at think tank Hoover Institution, said the United States is at a crossroads with China. It could define America’s security and the international order for decades to come. Here’s the latest blog on trade tensions between the U.S. and China. “Tensions ... » read more

The Long And Detailed Road To Automotive Compliance


Compliance with automotive safety requirements is slowing down both innovation and participation by a flurry of startups as the whole ecosystem struggles to bring autonomous vehicles to reality. This is particularly onerous for chipmakers, which face a high bar for IC integrity and reliability. They must meet specifications and be free of design errors. Improper behavior in corner-case s... » read more

A Comprehensive Approach To System-Level ESD


The performance and reliability of an electronics system largely depend on the system’s immunity from an electrostatic discharge (ESD) event. Because the components, custom chips and package come from various sources — and often from different companies — they are usually designed by separate teams working in silos and in accordance with predefined margins. The ESD Association estimates t... » read more

Process Variation And Aging


Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; and Naseer Khan, vice president of sales at M... » read more

Aging In Advanced Nodes


Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Design Rule Complexity Rising


Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

Functional Safety Methodologies For Automotive Applications


Safety-critical automotive applications have stringent demands for functional safety and reliability. Traditionally, functional safety requirements have been managed by car manufacturers and system providers. However, with the increasing complexity of electronics involved, the responsibility of addressing functional safety is now propagating through the supply chain to semiconductor companies a... » read more

Multiphysics Reliability Signoff For Next-Gen Auto Electronics Systems


The automotive industry is in the midst of a sea change. Growing market needs for electrification, connectivity on the go, advanced driver assistance systems, and ultimately the goal of autonomous driving, are creating newer requirements and greater challenges. A chassis on four wheels is now fitted with cameras, radar and other sensors, which will be the eyes of the driverless car, as well as ... » read more

A Reliability Baseline Is Essential For Today’s Complex IC Designs


Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

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