Big Data, Big Opportunities

By Jens Andersen - 25 Jun, 2015 - Comments: 0

For the last two decades I have spent a lot of my time managing operations and sales for several EDA startups, most of which were acquired. The focus of many of these companies was to provide solutions to optimize complex designs. We worked to enhance many of the top 25 semiconductor companies’ physical implementation flows using cutting edge technologies and methodologies to improve power, p... » read more

IP Integration Challenges Increase

By Ed Sperling - 24 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

Managing Dynamic Power

By Ann Mutschler - 16 Jun, 2015 - Comments: 0

Working with finFETs is a study in contrasts. While leakage is now under control for the first time in several process generations due to the advent of different gate technology, dynamic power density caused by tightly packed transistors and higher clock speeds has become the big issue. “FinFET technology helps with reducing static/leakage power so when your logic is not active, you can sh... » read more

IP Integration Challenges Increase

By Ed Sperling - 16 Jun, 2015 - Comments: 0

The Week In Review: Design/IoT

By Jesse Allen - 05 Jun, 2015 - Comments: 0

Tools Cadence unveiled Genus, their next-generation RTL synthesis and physical synthesis engine incorporating a multi-level massively parallel architecture and physically aware context-generation capability. Using it for their recent PowerVR GE7800 GPU, Imagination reported a 5X improvement in turnaround time versus the previous Cadence synthesis solution with no impact on power, performance... » read more

IP Market Shifts Direction

By Ed Sperling - 03 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at [getentity id="22035" e_name="Synopsys"]; Kurt Shuler, vice president of marketing at [getentity i... » read more

Memory Design At 16/14nm

By Brian Bailey - 28 May, 2015 - Comments: 0

As we get older the memory may start to fade, but that is not a viable option if we are talking about embedded memory. Chips contain increasing amounts of memory, and for many designs memory consumes more than half of the total chip area. “At 28nm we saw a few people with greater than 400Mbits of memory on chip,” says Prasad Saggurti, product marketing manager for Embedded Memory IP at [... » read more

Executive Insight: Jack Harding

By Ed Sperling - 28 May, 2015 - Comments: 0

SE: What's changed over the past 12 months? Harding: My starting point these days is around consolidation. At last count there were about 85 companies in the semiconductor industry. My bet is that at this time next year there will be about 70. The size of deal will not matter. Nothing will be too big. The strategic question is whether you're playing musical chairs and when the music stops, ... » read more

It’s Not What You Own, It’s What You Know

By Mike Gianfagna - 28 May, 2015 - Comments: 0

Shifting business models can change the rules. The ecosystems that define our manufacturing, procurement and delivery processes, along with the customer buying behaviors associated with those processes, can shift dramatically over time, resulting in a world that seems to be upside down at first glance. The exodus of mainstream manufacturing out of certain countries is an example of these shifts... » read more

Design Virtualization And Its Impact On SoC Design

By eSilicon - 27 May, 2015 - Comments: 0

At advanced technology nodes (40nm and below), the number of options that a system-on-chip (SoC) designer faces is exploding. Choosing the correct combination of these options can have a dramatic impact on the quality, performance, cost and schedule of the final SoC. Using conventional design methodologies, it is very difficult to know if the correct options have been chosen. There is simply ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: eSilicon

Big Data, Big Opportunities

IP Integration Challenges Increase

Managing Dynamic Power

IP Integration Challenges Increase

The Week In Review: Design/IoT

IP Market Shifts Direction

Memory Design At 16/14nm

Executive Insight: Jack Harding

It’s Not What You Own, It’s What You Know

Design Virtualization And Its Impact On SoC Design