3D Stacking: A Reality Check

By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ed Sperling The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013. While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law. But unlike the progres... » read more

Executive Briefing: Jack Harding

By Ed Sperling - 03 Jun, 2011 - Comments: 0

eSilicon's CEO talks with System-Level Design about changes in design at advanced nodes, the power of 2.5D and 3D stacking, and how the semiconductor supply chain is changing. [youtube vid=HlipMzgdksc] » read more

Who’s In Control?

By Ed Sperling - 26 May, 2011 - Comments: 0

By Ed Sperling A power shift is under way across the SoC world that ultimately determine who wins the business, who gets the biggest share and what technologies are ultimately used to get there. Complexity has reached a point where being able to pull the necessary pieces from a disaggregated supply chain is becoming much more difficult. That helps explain why all three of the major EDA comp... » read more

The Upside Of Dark Silicon

By Ed Sperling - 26 May, 2011 - Comments: 0

By Ed Sperling For many years the real challenge in IC design was in shrinking the components and features on a piece of silicon without burning up the chip or destroying signal integrity. Chipmakers have become quite adept at this over the past few decades. Too good, in fact. Now they are faced with a different kind of problem—what to do with all that extra silicon. Just as the long dist... » read more

The Future Of ASICS In 3D

By Javier DeLaCruz - 26 May, 2011 - Comments: 0

By Javier DeLaCruz 3D technology is generating a lot of interest as a way to reduce NRE costs and speed time to market. This is still a nascent approach, so people are looking for a single standard in through-silicon vias (TSVs), primarily to reduce infrastructure costs. Unfortunately, I do not think this will be possible. There are at least two fundamentally different applications for 3D t... » read more

SoC Ecosystems Become More Tightly Integrated

By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling SoC ecosystems are changing. Quality and focus are replacing volumes of names as companies that fund them begin to narrow down which partners add the most value and which markets they need to target. Establishing a ring of allies is nothing new, of course. IBM had its circle of most trusted software partners back in the 1970s when mainframes were the dominant computing platfo... » read more

Turning Chaos Into Order

By Jack Harding - 27 Apr, 2011 - Comments: 0

By Jack Harding It would be unthinkable to begin this article without recognition of the disaster the Japanese people are enduring, even as this is written. My friends and colleagues are as safe as they can be, so far; thousands are lost. But it takes no imagination to appreciate the psychological and very real overhang of nuclear toxins changing a society for a decade. The sad irony of the... » read more

Experts At The Table: Billion-Gate Design Challenges

By Ed Sperling - 01 Apr, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss billion-gate design challenges with Charles Janac, CEO of Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. What follows are excer... » read more

The Quest For A Better IP Integration Methodology

By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

The Current State Of 3D Stacking

By Javier DeLaCruz - 31 Mar, 2011 - Comments: 0

By Javier DeLaCruz Thru-silicon-vias (TSVs) have become a very hot topic in in recent months. Ever since Xilinx reported that it is using a 2.5D TSV approach for its Virtex-7 FPGAs the industry started to salivate with the prospects of this new technology. While this technology may be accessible for larger stacked memory, FPGAs, MEMS devices, and CMOS image sensors, this does not inherently me... » read more

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