tag: eSilicon

Week In Review: Design, Low Power
By Jesse Allen - 21 Sep, 2018 - Comments: 0

Tools & IP Cadence unveiled deep neural-network accelerator (DNA) AI processor IP, Tensilica DNA 100, targeted at on-device neural network inference applications. The processor is scalable from 0.5 TMAC (Tera multiply-accumulate) to 12 TMACs, or 100s of TMACs with multiple processors stacked, and the company claims it delivers up to 4.7X better performance and up to 2.3X more performance p... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Sep, 2018 - Comments: 0

M&A Intel acquired NetSpeed Systems, a network-on-a-chip and interconnect fabric IP and tool provider. Founded in 2011, the San Jose-based company recently put a focus on interconnects designed with AI applications in mind. Intel has cast the acquisition as a way to tie a number of its other technologies together. The team will join Intel's Silicon Engineering Group. Intel has been a NetSp... » read more

Processing In Memory
By Ed Sperling - 05 Sep, 2018 - Comments: 1

Adding processing directly into memory is getting a serious look, particularly for applications where the volume of data is so large that moving it back and forth between various memories and processors requires too much energy and time. The idea of inserting processors into memory has cropped up intermittently over the past decade as a possible future direction, but it was dismissed as an e... » read more

Energy-Efficient AI
By Ed Sperling - 30 Aug, 2018 - Comments: 1

Carlos Maciàn, senior director of innovation for eSilicon EMEA, talks about how to improve the efficiency of AI operations by focusing on the individual operations, including data transport, computation and memory. https://youtu.be/A3p_w7ENefs » read more

Big Changes For Mainstream Chip Architectures
By Ed Sperling - 23 Aug, 2018 - Comments: 3

Chipmakers are working on new architectures that significantly increase the amount of data that can be processed per watt and per clock cycle, setting the stage for one of the biggest shifts in chip architectures in decades. All of the major chipmakers and systems vendors are changing direction, setting off an architectural race that includes everything from how data is read and written in m... » read more

The New Deep Learning Memory Architectures You Should Know About
By eSilicon - 22 Aug, 2018 - Comments: 0

Artificial intelligence (AI) has come a long way. While our parents grew up with the dream to one day roam with robots, today we are interviewing Sophia, a citizen of Saudi Arabia, who is also the first humanoid robot to be granted a citizenship in any country. Deep learning, a brain-inspired discipline of AI has been around for a long time but has only recently taken off due to abundant data, ... » read more

Big Shifts In Tech Conferences
By Ed Sperling - 16 Aug, 2018 - Comments: 0

By Ed Sperling and Katherine Derbyshire Identifying central themes in technology conferences, or finding enough latitude where the theme is extremely well defined, is becoming challenging throughout the tech industry. Throughout the semiconductor industry, in particular, many are asking how various organizations will differentiate conferences in the future and who will be the target audience... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 Aug, 2018 - Comments: 0

Achronix and Mentor uncorked an optimized HLS flow for Achronix's FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor's Catapult HLS and Achronix's ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve QoR, it is suitable for any design targeting Achronix techn... » read more

More Sigmas In Auto Chips
By Ann Mutschler - 02 Aug, 2018 - Comments: 0

The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems. This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these d... » read more

Pros, Cons Of ML-Specific Chips
By Ed Sperling - 27 Jul, 2018 - Comments: 1

Semiconductor Engineering sat down with Rob Aitken, an Arm fellow; Raik Brinkmann, CEO of OneSpin Solutions; Patrick Soheili, vice president of business and corporate development at eSilicon; and Chris Rowen, CEO of Babblelabs. What follows are excerpts of that conversation. To view part one, click here. Part two is here. SE: Is the industry's knowledge of machine learning keeping up with th... » read more

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