tag: etch

How Metrology Tools Stack Up In 3D NAND Devices
By Laura Peters - 15 May, 2023 - Comments: 0

Multiple innovations in semiconductor processing are needed to enable 3D NAND bit density increases of about 30% per year at ever-decreasing cost per bit, all of which will be required to meet the nonvolatile storage needs of the big data era. 3D NAND is the first truly three-dimensional device in production. It is both a technology driver for new metrology methods and a significant part of ... » read more

A Deposition And Etch Technique To Lower Resistance Of Semiconductor Metal Lines
By Timothy Yang - 20 Apr, 2023 - Comments: 0

Copper's resistivity depends on its crystal structure, void volume, grain boundaries and material interface mismatch, which becomes more significant at smaller scales. The formation of copper (Cu) wires is traditionally done by etching a trench pattern in low-k silicon dioxide using a trench etch process, and subsequently filling the trench with Cu via a damascene flow. Unfortunately, this meth... » read more

Research Bits: April 4
By Jesse Allen - 04 Apr, 2023 - Comments: 0

Wet-like plasma etching Researchers from Nagoya University and Hitachi developed a new etch method called wet-like plasma etching that combines the selectivity of wet etching with the controllability of dry etching. The researchers say the technique will make it possible to etch complex structures such as metal carbides consisting of titanium (Ti) and aluminum (Al), such as TiC or TiAlC, wh... » read more

Process Innovations Enabling Next-Gen SoCs and Memories
By Laura Peters - 20 Feb, 2023 - Comments: 0

Achieving improvements in performance in advanced SoCs and packages — those used in mobile applications, data centers, and AI — will require complex and potentially costly changes in architectures, materials, and core manufacturing processes. Among the options under consideration are new compute architectures, different materials, including thinner barrier layers and those with higher th... » read more

Making Chips Yield Faster At Leading-Edge Nodes
By Ed Sperling - 30 Nov, 2022 - Comments: 0

Simulation for semiconductor manufacturing is heating up, particularly at the most advanced nodes where data needs to be analyzed in the context of factors such as variation and defectivity rates. Semiconductor Engineering sat down with David Fried, corporate vice president of computational products at Lam Research, to talk about what's behind Lam's recent acquisition of Esgee Technologies, ... » read more

What’s Different About Next-Gen Transistors
By Katherine Derbyshire - 20 Oct, 2022 - Comments: 0

After nearly a decade and five major nodes, along with a slew of half-nodes, the semiconductor manufacturing industry will begin transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures at the 3nm technology node. Relative to finFETs, nanosheet transistors deliver more drive current by increasing channel widths in the same circuit footprint. The gate-all-aroun... » read more

Chipmaking In The Third Dimension
By Krishnan Shrinivasan - 16 Jun, 2022 - Comments: 0

Every few months, new and improved electronics are introduced. They’re typically smaller, smarter, faster, have more bandwidth, are more power-efficient, etc. — all thanks to a new generation of advanced chips and processors. Our digital society has come to expect this steady drip of new devices as sure as the sun will rise tomorrow. Behind the scenes, however, engineers are working feve... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips
By Mark LaPedus - 21 Mar, 2022 - Comments: 0

Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

Wirebond IC Substrates: Challenges Ahead
By Prasad Dhond - 17 Mar, 2022 - Comments: 0

Substrate suppliers are slashing capacity allocated to wirebond IC substrates. We hear about "limited tenting capacity," "no support for EBS designs," and requests for "conversion to etchback" designs. What does all this mean? Let's start with "Line" and "Space." "Line" is the width of a trace on a substrate and "Space" is the distance between the two traces. For wirebond packages such a... » read more

Precision Selective Etch And The Path To 3D
By Vahid Vahedi - 17 Mar, 2022 - Comments: 0

Scaling (the shrinking of the tiny devices in chips such as transistors and memory cells) has never been easy, but making the next generation of advanced logic and memory devices a reality requires creating new structures at the atomic scale. When working with dimensions this small, there is little room for variation. Compounding the problem is a need to remove material isotropically, or, un... » read more

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