Wirebond IC Substrates: Challenges Ahead

Choosing the right substrate design and surface plating process is key to ensuring supplier support.


Substrate suppliers are slashing capacity allocated to wirebond IC substrates. We hear about “limited tenting capacity,” “no support for EBS designs,” and requests for “conversion to etchback” designs. What does all this mean?

Let’s start with “Line” and “Space.” “Line” is the width of a trace on a substrate and “Space” is the distance between the two traces. For wirebond packages such as CABGA or PBGA, the substrate line/space requirements are more relaxed compared to flip chip packages like FCBGA or fcCSP. This makes sense as the applications supported by CABGA such as MCUs are less demanding than high performance processors packaged in FCBGA.

Substrates use different patterning and plating methods based on line/space and interconnects.

Let’s start with patterning methods.


Patterning is the process used to create copper traces and other interconnects on the substrate.

Subtractive or Tenting Process

Subtractive patterning is most used for wirebond BGA substrates where line/space requirements are >35/35 um. The starting point is a copper clad laminate (CCL) core. It consists of a laminate material with thin copper foil on both sides.

Vias are drilled into the core as needed by the design.

This core with vias is first coated with a thin layer of copper using an electroless plating process so that a conducting path is established for electrolytic plating in the following steps.

Next, we use electrolytic plating to deposit thicker copper onto the substrate.

Areas where interconnects are to be formed (i.e. copper needs to be kept) are covered with dry film.

The unwanted copper is etched away leaving behind traces that connect pads to one another.

Since unwanted copper is stripped away, this is known as a subtractive process. The etchant must etch through three layers with different thicknesses – the Cu foil, the electroless Cu and electrolytic copper. The etchant acts differently on each of these layers, resulting in a non-uniform shape that resembles a tent when viewed in a cross section. Hence this process is also known as tenting.

The above process steps are then repeated to create additional layers on the substrate.

Additive Process

The subtractive process is a lower cost process, but the thick electrolytic copper layer is difficult to etch through. Achieving features with finer features is difficult using the subtractive process. In an additive process, the Cu traces are “added” using an electrolytic plating process. A Semi Additive Process (SAP) is neither purely additive (which requires no etching) nor purely subtractive (where only etching of thick Cu is performed) (1).

Modified Semi Additive Process (MSAP)

In the MSAP process, the copper clad laminate core is plated with a thin layer of copper using an electroless process. Dry film is then applied to areas that don’t need to be interconnected. This is followed by electrolytic plating to add in the interconnects. The dry film and unwanted copper are then stripped out, leaving the desired circuit pattern on the substrate.

Semi Additive Process (SAP)

SAP is used for flip chip substrates that use ABF (Ajinomoto Build-up Film). These build-up layers do not have copper foil. This allows for even finer features on the substrate. They follow the same patterning process as MSAP otherwise.

Surface finish for wirebond substrates

The interconnect area on the top surface (bond fingers/pads) and BGA pads on the bottom surface must be plated to prevent oxidation and provide a reliable interconnect.

The choice of surface finish is determined by many factors such as interconnect method (wirebond, flip chip bump, etc.), signal speeds, desired substrate size, and density of circuit design. Flip chip substrates use electroless plating methods such as Organic Solderability Protectant (OSP) and Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG). For Wirebond BGA substrates, the standard finish for bond fingers and BGA pads is Ni/Au which is plated using an electrolytic process. In some cases, OSP finish can be used on the BGA side, but ENEPIG has potential hurdles with Cu wire bondability. This makes electrolytic surface plating the key process used for wirebond substrates.

Electrolytic surface plating

An electrolytic plating process requires a conducting path to the areas that need to be plated. Each of the following methods provides a different way to create this conduction path.

1) Standard Bussed Substrates

This method uses dedicated bus lines (plating stubs) to pass electric current to each pad that requires plating. The advantage is that it is a simple process. However, the substrate becomes larger, and the design cannot be very dense as it must accommodate the bus traces.

2) Etchback

This method connects the pads and bond fingers to be plated using plating bus lines that are later disconnected by selective etching, hence the name “etchback.” This process allows a more compact design than the standard bussed design, but still requires looser spacing between the plating bus lines and other features (vias, signal traces, etc.) to prevent issues such as copper migration.

3) Modified Electrolytic Bussless Substrate (MEBS)

MEBS uses Ni/Au plating on the bond fingers but uses Organic Solderability Protectant (OSP) on the solder ball pads. For MEBS designs, the bottom BGA pads are connected to bond fingers on the top layer. During processing, the entire bottom BGA layer is plated with Electroless Copper and the electric current is passed to plate the bond fingers on the top layer. The Cu plating from the bottom layer is now removed and the pads are coated with OSP.

4) Electrolytic Bussless Substrate (EBS)

The EBS method doesn’t use a plating bus. Instead, an electroless plating step followed by patterning creates connections to the pads and bond fingers that need to be plated. The EBS method allows for a dense, compact, and optimized design. The bond fingers (top side of substrate) as well as BGA pad (bottom side of substrate) are plated with NiAu.

However, EBS involves several additional process steps and substrate suppliers are reluctant to allocate capacity to EBS designs. It is difficult to tool up an EBS substrate in today’s constrained environment.


Wirebond BGA demand continues to be strong with growth in microcontroller and touch controller applications. However, traditional substrate suppliers are reducing capacity allocated to these substrates. Standard and etchback designs are easier to support from a process standpoint, whereas EBS and MEBS are more difficult. Choosing the right substrate design and surface plating process is key to ensuring supplier support. Only a few substrate suppliers are planning to expand support to wirebond BGA substrates and engagements with newer suppliers who are willing to invest will be critical in the future.


  1. Tummala, Rao R. (2019). Fundamentals of Device and Systems Packaging (2nd Edition). McGraw Hill

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