tag: ETH Zurich

Quantum: Loophole-​Free Bell Test with Superconducting Circuits (ETH Zurich)
By Technical Paper Link - 10 May, 2023 - Comments: 0

A new technical paper titled "Loophole-free Bell inequality violation with superconducting circuits" was published by a group of researchers led by ETH Zurich. Abstract (partial) "Here we demonstrate a loophole-free violation of Bell’s inequality with superconducting circuits, which are a prime contender for realizing quantum computing technology. To evaluate a Clauser–Horne–Shimony... » read more

Chip Industry’s Technical Paper Roundup: Apr. 25
By Linda Christensen - 25 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=94 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

CAN Bus Security Using TDCs (ETH Zurich & CISPA Helmholtz Center)
By Technical Paper Link - 21 Apr, 2023 - Comments: 0

A technical paper titled "EdgeTDC: On the Security of Time Difference of Arrival Measurements in CAN Bus Systems" was published by researchers at ETH Zurich and CISPA Helmholtz Center for Information Security. Abstract "A Controller Area Network (CAN bus) is a message- based protocol for intra-vehicle communication designed mainly with robustness and safety in mind. In real-world deployment... » read more

State of the Art And Future Directions of Rowhammer (ETH Zurich)
By Technical Paper Link - 18 Apr, 2023 - Comments: 0

A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon in... » read more

Chip Industry’s Technical Paper Roundup: Apr. 18
By Linda Christensen - 18 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=93 /]   If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involv... » read more

Scalable, Shared-L1-Memory Manycore RISC-V System
By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory" was published by researchers at ETH Zurich and University of Bologna. Abstract: "Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common belief that these tightly... » read more

Chip Industry’s Technical Paper Roundup: Apr. 10
By Linda Christensen - 10 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=92 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Low-Power Heterogeneous Compute Cluster For TinyML DNN Inference And On-Chip Training
By Technical Paper Link - 09 Apr, 2023 - Comments: 0

A new technical paper titled "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training" was published by researchers at University of Bologna and ETH Zurich. Abstract "On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clus... » read more

Chip Industry’s Technical Paper Roundup: Mar. 21
By Linda Christensen - 21 Mar, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=88 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

FPGA-based Infrastructure, With RISC-V Prototype, to Enable Implementation & Evaluation of Cross-Layer Techniques in Real HW (Best Paper Award)
By Technical Paper Link - 15 Mar, 2023 - Comments: 0

A technical paper titled "MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations" was published by researchers at University of Toronto, ETH Zurich, and Carnegie Mellon University. This paper won the Best Paper Award at the HiPEAC 2023 conference. Abstract: "This paper introduces the first open-source FPGA-based infrastructure, MetaSy... » read more

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