tag: EUV

Math Questions
By Ed Sperling - 08 Feb, 2013 - Comments: 0

The race is on. GlobalFoundries, TSMC, Samsung, IBM and Intel are all neck deep in research, test chips, variability, lithography and three-dimensional transistor designs. For the first time, though, the goal very publicly has shifted from performance and area to energy efficiency. Being able to double battery life with existing performance over the next couple nodes could mean smart phones ... » read more

Supersizing Wafers
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Katherine Derbyshire Get ready for 450mm wafers. First seriously considered in 2005, these supersized wafers, along with the equipment to handle, measure, and process them, have gradually made their way to the top of the semiconductor industry’s priority list. But what exactly does that mean? What will 450mm fabs look like, and how will they differ from the 300-mm fabs being built toda... » read more

Reducing The Drama In DFM
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes. The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, se... » read more

Facing Up To RC Delay
By Ed Sperling - 15 Nov, 2012 - Comments: 0

y Ed Sperling Resistance and capacitance delays have always been someone else’s problem to solve at some fuzzy process node in the future, and for the most part manufacturers and equipment makers have done a wizard-like job of making this problem go away. They can’t make it disappear anymore, though, and beginning at 14nm and beyond RC delay is becoming more than just an annoyance. The ... » read more

Experts At The Table: Issues In Lithography
By Ed Sperling - 05 Nov, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation. SMD: What is the general state of the next-genera... » read more

Experts At The Table: Issues In Lithography
By Ed Sperling - 29 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation. (Part one can be found here.) SMD: Let’s re-vi... » read more

Moore’s Law Revisited
By Ed Sperling - 25 Oct, 2012 - Comments: 0

It’s no surprise that Moore’s Law can continue for many more generations. Intel’s road map already extends down to 5nm, most likely with carbon nanotube FETs, tunnel FETs, graphene TSVs and maybe even fully depleted SOI to replace bulk CMOS. The rest of the industry has been hanging back a node or two, gliding on the coattails of what Intel and companies like IBM, Samsung and STMicroel... » read more

Challenges Grow For EUV
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus In the late 1990s, a group led by Intel launched a consortium to propel extreme ultraviolet (EUV) lithography into the mainstream. Originally, the consortium, dubbed the EUV LLC, envisioned the advent of EUV scanners that would move into production at the 65nm node. Clearly, the now-defunct consortium underestimated the difficulties and challenges associated with EUV. ASM... » read more

Beam Me Up
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus For years, electron-beam tools have been struggling to keep up with photomask complexity, causing an alarming increase in write times and mask production costs. Intel and others recently warned that e-beams soon could reach their fundamental limits, thereby requiring the need for new solutions. And in the multiple patterning era, mask makers could see their capital costs soa... » read more

Behind The Mask
By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss the current and future photomask manufacturing challenges with Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks, one of the world’s largest merchant mask makers. SMD: The outlook for the photomask industry is for 2% growth in 2012. Do you agree with that? Kalk: That’s ... » read more

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