tag: fan-outs

The 200mm Equipment Scramble
By Ed Sperling - 23 Aug, 2017 - Comments: 0

An explosion in 200mm demand has set off a frenzied search for used semiconductor manufacturing equipment that can be used at older process nodes. The problem is there is not enough used equipment available, and not all of the new or expanding 200mm fabs can afford to pay the premium for refurbished or new equipment. This may sound like a straightforward supply and demand issue, but behind t... » read more

Packaging Enters New Phase
By Ed Sperling - 07 Aug, 2017 - Comments: 0

The race is on to make advanced packaging less expensive than shrinking everything down onto the same die—much less expensive, in fact. Following several years of speculation and rather shaky market predictions at the beginning of this decade, packaging houses and foundries spent the last four years proving that packaging really does provide a viable alternative to shrinking die in terms o... » read more

Advanced Packaging Moves To Cars
By Ann Mutschler - 07 Aug, 2017 - Comments: 0

By Ann Steffora Mutschler and Ed Sperling As automotive OEMs come up to speed on electrification of vehicles, each at their own pace, they are starting to embrace novel packaging approaches as a way to differentiate themselves in an increasingly competitive market. Wirebond used to dominate this market, where most of the chips were relatively unsophisticated and product cycles were slow�... » read more

Is 7nm The Last Major Node?
By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

Shrink Or Package?
By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

Primer On Packaging
By Lam Research - 15 Jun, 2017 - Comments: 0

Ever open the body of your smartphone (perhaps unintentionally) and see small, black rectangles stuck on a circuit board? Those black rectangles are packaged chips. The external chip structure protects the fragile integrated circuits inside, as well as dissipates heat, keeps chips isolated from each other, and, importantly, provides connection to the circuit board and other elements. The manufa... » read more

What’s Next In Scaling, Stacking
By Mark LaPedus - 05 Jun, 2017 - Comments: 9

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

Electroplating IC Packages
By Mark LaPedus - 10 Apr, 2017 - Comments: 2

The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp. [getentity id="22817" e_name="Applied Materials"]  recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging. ECD—sometimes referred to as pl... » read more

Power Impacting Cost Of Chips
By Brian Bailey - 15 Mar, 2017 - Comments: 0

The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

Crossing The Chasm: Uniting SoC And Package Verification
By Tarek Ramadan - 06 Mar, 2017 - Comments: 0

Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, and foundries must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.... » read more

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