tag: FPGAs

FPGA Verification with Assertions: Why Bother?
By Mentor, a Siemens Business - 17 Dec, 2014 - Comments: 0

This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions. To read more, click here. » read more

Hybrid Verification: The Only Way Forward
By Brian Bailey - 20 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Blog Review: Nov. 5
By Ed Sperling - 05 Nov, 2014 - Comments: 0

Cadence's Brian Fuller zeroes in on ISO 26262, the automotive safety standard that's supposed to guard against nightmare failures in your car. Hopefully it works. They won't protect against cyber terrorism, though. Rambus' Aharon Etengoff takes a look at the challenges of connected vehicles. Mentor's J. Van Domelen looks at NASA's increased reliance on commercial partners, which has not b... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores
By Synopsys - 24 Sep, 2014 - Comments: 0

This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

New Winners And Losers
By Brian Bailey - 24 Jul, 2014 - Comments: 0

During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of [getkc id="74" comment="Moore's Law"]. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?” Colwell believes that power is the primary reason why... » read more

Productive Clock Domain Crossing Verification
By Kiran Vittal - 08 May, 2014 - Comments: 2

Recently, we were invited to participate in an internal Chips@Cisco event along with other EDA vendors and FPGA providers. Executives from these vendors participated in a panel to discuss the challenges seen by the technology leaders in FPGAs and what it means to the industry. Everyone on the panel agreed that design size and complexity, including clock domains, is continuing to follow Moore’... » read more

Google Project Ara And The Low-Power Imperative
By Brian Fuller - 08 May, 2014 - Comments: 2

You’ve no doubt seen the slides: 50 billion Internet of Things (IoT) devices by 2020. That’s an amazing number, but consider this: What if they each draw 1W? All things begin equal, we’d have to build another 50 nuclear power plants in the world to handle that additional energy requirement. (Something tells me that outcome is unrealistic). Power takes center stage as we evolve into ... » read more

Blog Review: April 9
By Ed Sperling - 09 Apr, 2014 - Comments: 0

Mentor’s Colin Walls discovered an interesting video of the software programming learning process—a teacher responding literally to commands from his students on how to make a jam sandwich. It’s harder than it looks. Cadence’s Brian Fuller captures a speech by his colleague, Sanjiv Taneja, about the need for a comprehensive verification approach and smart IP reuse. The overriding th... » read more

System Bits: Feb. 4
By Ann Mutschler - 04 Feb, 2014 - Comments: 0

Speeding Access To Information Big data today is usually stored on multiple hard disks on a number of machines across an Ethernet network, but this storage architecture considerably increases the time it takes to access the information. Researchers at MIT have developed a storage system for big-data analytics they claim can dramatically reduce the time it takes to access information. The sy... » read more

SpyGlass Flow For Xilinx FPGA
By Various Writers - 04 Dec, 2013 - Comments: 0

As the cost of doing ASIC design skyrockets, FPGAs are becoming an attractive alternative for system-on-chip (SoC) types of design. Large numbers of increasingly complex designs are now done with FPGAs, making verification a major task. Besides the usual issues of width mismatch, connectivity or synthesis-simulation mismatch, there are also problems related to multiple asynchronous clock domain... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy